Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-09
2001-05-15
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06232632
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device containing non-volatile memory cells and to a method of making such a semiconductor device. The present invention has particular applicability in manufacturing ultra large scale integration and high density non-volatile semiconductor devices with deep sub micron features and active regions isolated by insulated trenches.
BACKGROUND ART
Conventional non-volatile semiconductor devices include various types of flash memory devices, electrically programmable read only memory (EPROM) devices and electrically erasable programmable read only memory (EEPROM) devices. Such conventional types of memory devices are generally characterized by a floating gate and an electrical connection called a control gate, typically fabricated from polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive, e., phosphorous. The floating gate is separated from a substrate region by a gate dielectric or tunnel dielectric layer of insulating material while the substrate region includes symmetrical or asymmetrical source/drain regions defining a channel region therebetween. The floating gate and control gate are typically separated by a layer of insulating material characterized as an interpoly dielectric layer.
EEPROMs are typically programmed by applying a voltage to the control gate so that electrons or a charge tunnel through the tunnel oxide layer and is stored on the floating gate in a capacitive manner. Erasing is implemented by grounding the control gate and causing electrons or charge to tunnel through the tunnel dielectric layer to the substrate. Typically, electrons tunnel through the tunnel dielectric layer by a phenomenon called “Fowler-Nordheim” tunneling. A conventional EEPROM is disclosed by Mukherjee et al., U.S. Pat. No. 4,868,619 and comprises an asymmetrical drain-source junction.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices requires design rules of 0.18 microns and under, increased transistor and circuit speeds, sharp junctions, high reliability and increased manufacturing throughput for competitiveness. The reduction of design rules to 0.18 microns and under generates numerous problems challenging the limitations of conventional semiconductor technology.
Non-volatile memory cells occupy a significant amount of precious real estate on a semiconductor substrate and, hence, pose a serious impediment to miniaturization. Moreover, the protrusion of the gate electrodes above the main surface of a substrate results in the formation of a significant step portion which is difficult to planarize, thereby challenging the depth of focus limitations of conventional photolithographic techniques.
In copending U.S. patent application Ser. No. 08/882,961 filed on Dec. 18, 1997 and in copending application Ser. No. 08/993,890 filed on Dec. 18, 1997, semiconductor devices are disclosed comprising dual non-volatile memory cells, each comprising a substantially U-shaped floating gate electrode in a trench formed in the semiconductor substrate and a substantially T-shaped control gate electrode filling the trench and extending on the substrate.
In copending U.S. patent application Ser. No. 09/026,358 filed on Feb. 19, 1998, a semiconductor device containing double density non-volatile memory cells is disclosed, wherein each double density non-volatile memory cell contains a floating gate within a trench formed in a substrate and a control gate formed thereon.
There exists a continuing need for semiconductor devices with increased density and highly reliable deep sub-micron features. There exists a particularly need for reliable semiconductor devices containing dense non-volatile memory cells with increased channel lengths.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a non-volatile semiconductor device having improved device scalability, reduced complexity and low power programming and erasing.
Another advantage of the present invention is a method of manufacturing a non-volatile semiconductor device having improved device scalability, reduced complexity and low power programming and erasing.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device comprising: a substrate; and first and second spaced apart double non-volatile memory cells, each double non-volatile memory cell comprising first and second floating gate electrodes spaced apart from a common control gate electrode by a dielectric layer.
Another advantage of the present invention is a semiconductor device comprising: a substrate having a main surface; and first and second spaced apart double non-volatile memory cells, each memory cell comprising: a trench extending from the main surface into a common source region; a tunnel oxide layer lining the trench; first and second floating gates within the trench; and a common control gate electrode comprising a first section extending through each trench between the first and second floating gate electrodes with a dielectric layer therebetween, the first section having a bottom surface terminating below the common source region, and a second section integral with the first section, extending substantially laterally on the upper surface of the first and second floating gates with the dielectric layer therebetween.
Another advantage of the present invention is a method of manufacturing a semiconductor device, the method comprising forming first and second spaced apart double non-volatile memory cells, a portion of each of which extends into a substrate, each double non-volatile memory cell comprising first and second floating gate electrodes spaced apart from a common control gate by a dielectric layer.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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patent: 5049956 (1991-09-01), Yoshida et al.
patent: 5053839 (1991-10-01), Esquivel et al.
patent: 5338953 (1994-08-01), Wake
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patent: 5936274 (1999-08-01), Forbes et al.
patent: 5945708 (1999-08-01), Tihanyi
patent: 6020227 (2000-02-01), Bulucea
patent: 6022779 (2000-02-01), Shin et al.
patent: 6093606 (2000-07-01), Lin et al.
patent: 6124168 (2000-09-01), Ong
Advanced Micro Devices , Inc.
Nguyen Cuong Q.
Thomas Tom
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