Double data rate synchronous memory with block-write

Details Double data rate synchronous memory with block-write Double data rate synchronous memory with block-write

1999-05-18

2003-05-06

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C365S230030, C365S230040, C365S230080

Reexamination Certificate

active

06560669

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention was made in attempting to solve specific problems in connection with computer memory devices. The problem being addressed by the inventor was that of improving the access and processing speed of memory devices using double data rate block-writes.
2. Description of the Related Art
To construct a video display of colored pixels, a computer creates a block of video data through a large number of memory writes. Since memory accesses are slower than many internal processor operations, creating the data blocks used in video applications entails substantial computer time. One direction for improving video applications involves decreasing the time needed to create blocks of video data in a memory.
FIG.
1
. shows a timing diagram
10
for input signals in one type of prior art memory device (not shown). A clock signal
12
synchronizes memory accesses associated with command
14
; address
16
, e.g., column, row and bank address; and data signals
18
. The memory device latches the command, address and data signals
14
,
16
,
18
on rising edges
20
,
22
,
24
,
26
of the clock signal
12
. The illustrated memory device latches the command, address, and data signals
28
,
30
,
32
on the same rising edge
20
, but other memory devices may have a latency period between the latching of the command/address signals and the data signal (not shown).
Referring still to
FIG. 1
, the memory device can latch one data signal, e.g., DATA m, DATA m+1, DATA m+2, DATA m+3, on the rising edge
20
,
22
,
24
,
26
of each of four clock cycles. Since the memory devices latches one packet of write data during each CLK signal, the memory illustrated by the timing diagram
10
is referred to as a memory device operating at a single data rate. During latency periods in which the memory device is executing a command, external signals for no new operation (NO-OP) may be received.
Some prior art memory devices can also perform block-writes. A block-write stores the same data to a block of memory locations, e.g., a number of adjacent column addresses, through a single write command. The use of block-writes can increase the effective speed of a memory device, which performs many write operations with the same data. Video applications frequently write the same data, e.g., a pixel color, to a large block of memory locations, i.e., to record the individual color pixels of an image. Block-writes can speed up video applications.
FIG. 2
shows a timing diagram
50
for external signals to a memory device (not shown) performing a block-write. The memory device latches a block-write command
52
, a block address
54
, and mask data
56
on a rising edge
58
of the clock signal
12
. The actual block-write occurs during a time period t
BW
subsequent to latching the block-write command
52
. The illustrated memory device can perform a block-write every two clock cycles, i.e., another block-write command can be latched t
BW
after latching the present block-write command.
The advantages of block-writes can be understood by comparing the ordinary write of
FIG. 1
to the block-write of FIG.
2
. If the block-write of
FIG. 2
stores data to 8 adjacent column addresses, the block-write writes an average of up to 4 memory locations per clock cycle, i.e., if subsequent block-writes are t
BW
apart. The ordinary write of
FIG. 1
writes up to one memory location per clock cycle, i.e., if subsequent writes are spaced by the time to complete a write burst. Thus, the 8-column block-write of
FIG. 2
has an effective write speed of up to 4 times the write speed of the ordinary write of FIG.
1
. Increasing the number of columns written through block-writes effectively increases the write speed of a memory.
A block-write writes to blocks of memory locations having a fixed size, e.g., a fixed number of adjacent column addresses. Employing mask data in conjunction with a block-write introduces flexibility into the size of the blocks written. The mask data disables a subset of the fixed number of memory locations of the block so that the block-write does not store new data to the disabled subset. For example, a 8-column block-write performed with an 8 binary-digit mask (00111101) would write data to columns
3
,
4
,
5
,
6
, and
8
of a chosen block of adjacent memory locations. Thus, the use of mask data enables the performance of selective block-writes.
The mask data may also be employed to disable selected bits or bytes within each memory location. The ratio of the size of the block written to the number of mask data bits determines the selectivity of a block-write. For example, a mask of 32 bits enables selectivity at the 1 byte level for an 8-column block-write to memory locations of 4 byte size. Masks provide a write selectivity determined by the size of the mask.
Since video applications often store each pixel of an image in a separate byte of memory, memory allocated for a video image may have different data stored in adjacent bytes. A masked block-write can store a video image to memory if the mask enables writing different data in adjacent bytes of memory, i.e., selectivity at the one byte-level. For a 16-column block-write to 4-byte memory locations be used in video applications, 64 bits have to be provided with each block-write command.
Memory devices having 32 bit wide data packets, could ordinarily provide 32 bits of mask data per clock cycle—an insufficient mask for the above-described video application. The usefulness of block-write in video memory devices would be increased if the size of the block could be increased without sacrificing selectivity.
The additional cost and complexity of implementing block-writes, as compared to other alternatives, may not be justified for the above-described effective speeds of 8-column block-writes. Nevertheless, the write speeds obtainable through the other alternatives substantially limit the speeds of video applications. Thus, further improvements to block-writes may enable faster video applications.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
A method and apparatus are provided to perform block-writes to a memory device. In a first aspect of the invention, the memory device includes a register adapted to store data for a block-write, a data input port to send data to the register, at least one memory bank, and a hardware device to block-write data from the register to the memory device. The data input port is incapable of receiving as many bits of data in parallel as the register sends to the memory bank during a block-write.
In a second aspect of the invention, the method for performing a block-write to a memory bank includes receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from the write logic unit to the memory bank at a double data rate. The clock cycle determines the data rate.
In a third aspect of the invention, a second memory device is provided including an input port capable of receiving mask data, and the memory device is adapted to perform a block-write with the mask data at a double data rate. In a fourth aspect of the invention, a second method to perform block-writes to a memory device is provided. The second method performs masked block-writes. The second method also includes writing mask data to a memory device at a double data rate and performing the masked block-writes using the mask data.


REFERENCES:
patent: 4816815 (1989-03-01), Yoshiba
patent: 5612922 (1997-03-01), McLaury
patent: 5659518 (1997-08-01), McLaury
patent: 5717904 (1998-02-01), Ehlers et al.
patent: 5740179 (1998-04-01), Dorney et al.
patent: 5781496 (1998-07-01), Pinkham et al.
patent: 5787046 (1998-07-01), Furuyama et al.
patent: 5956744 (1999-09-01), Robertson et al.
patent: 5991232 (1999-11-01), Matsumura

Affiliated with

Also associated with

Rating

Double data rate synchronous memory with block-write does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Double data rate synchronous memory with block-write, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double data rate synchronous memory with block-write will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3030745