Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-01-29
2001-12-11
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S101000, C711S102000, C711S103000, C711S104000, C711S150000, C711S167000, C711S168000
Reexamination Certificate
active
06330636
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to a double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device which incorporates a static random access memory (“SRAM”) cache per memory bank.
As the performance of computer central processing units (“CPUs”) has increased dramatically in recent years, this performance improvement has far exceeded that of any corresponding increase in the performance of computer main memory. Typically, main memory has been made up of numbers of asynchronous DRAM integrated circuits and it was not until the introduction of faster SRAM cache memory that the performance of systems with DRAM main memory improved. This performance improvement was achieved by making a high speed locally-accessed copy of memory available to the CPU so that even during memory accesses, the CPU would not always need to operate at the slower speeds of the system bus and the main memory DRAM. This method of copying memory is referred to as “caching” a memory system and is a technique made possible by virtue of the fact that much of the CPU accesses to memory is directed at localized memory address regions. Once such a region is copied from main memory to the cache, the CPU can access the cache through many bus cycles before needing to refresh the cache with a new memory address region. This method of memory copying is advantageous in memory Read cycles which, in contrast to Write cycles, have been shown to constitute 90% of the external accesses' of the CPU.
As mentioned previously, the most popular hardware realization of a cache memory employs a separate high-speed SRAM cache component and a slower but less expensive DRAM component. A proprietary Enhanced DRAM (EDRAM®) integrated circuit memory device, developed by Enhanced Memory Systems, Inc., assignee of the present invention, integrates both of these memory elements on one chip along with on-chip tag maintenance circuitry to further enhance performance of computer main memory over separate SRAM and DRAM components. Details of the EDRAM device are disclosed and claimed in U.S. Pat. Nos.: 5,699,317 issued Dec. 16, 1997 and 5,721,862 issued Feb. 24, 1998, both assigned to Enhanced Memory Systems, Inc., the disclosures of which are specifically incorporated herein by this reference.
SDRAMs differ from earlier asynchronous DRAM devices by incorporating two or more memory banks per device and by providing a simple, synchronously clocked interface in lieu of separate asynchronous clocking and discrete row and column access control lines. These differences result in a relatively higher data bandwidth and potentially faster access times for computer main memory which is particularly important with current and anticipated memory intensive multimedia and graphics applications.
The DRAM industry has also developed a double data rate version of the synchronous DRAM that doubles the peak data rate of the SDRAM by clocking data on both edges of the clock. Double data rate SDRAMs utilize a bi-directional data strobe to clock data to and from the memory device. The data strobe is clocked at the same time as the data and propagates over a bus which is designed to be substantially the same length and have the same capacitive loading as the data bus to minimize skew between the data strobe and the data signals.
However, like the SDRAM, the DDR SDRAM exhibits a relatively slow DRAM latency for activating the DRAM bank (row-to-column delay time “t
RCD
”) and accessing data from the sense amplifiers (column address strobe “CAS” latency). Since burst read data is accessed from the sense amplifiers, the row must remain activated until the burst is completed. This increases the latency to access another row on the next burst. The combination of long row access latency (t
RCD
+CAS latency) together with long page miss latency (precharge time “t
RP
” plus tRCD and CAS latency) results in poor bus efficiency when frequent page misses on random accesses occur. In addition, the current DDR SDRAM requires the bus to be idle (or unused) during all DRAM refresh operations thereby further degrading performance.
SUMMARY OF THE INVENTION
To ameliorate these conditions, a new DDR SDRAM architecture is disclosed herein that combines the benefits of Enhanced Memory Systems, Inc. EDRAM® architecture with that of a DDR SDRAM input/output architecture to effectively double peak bandwidth and maximize sustained bandwidth under normal random access conditions. In a preferred embodiment disclosed herein, the present invention proposes the use of a conventional four memory bank DDR SDRAM architecture with the addition of a row register cache (for example SRAM) per bank. A separate data path is provided in each bank to move write data directly to the DRAM sense amplifiers.
Particularly disclosed herein is a double data rate synchronous dynamic random access memory device having data, data strobe and address bus inputs thereto. The memory device comprises one or more memory arrays each having an associated sense amplifier, a designated row in a selected one or more of the memory arrays being accessed in accordance with address signals provided to one or more row decoders coupling each of the memory arrays to the address bus. One or more column decoders, each being associated with one or more of the memory arrays are coupled to receive the address signals for accessing a designated column in the selected one or more of the memory arrays. One or more caches, are respectively interposed between one of the column decoders and one or more of the memory arrays, whereby data to be written to the memory device on the data input is directed to the selected ones of the memory arrays and data to be read from the memory device is read from the caches in accordance with the address signals on the address bus.
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Sar
Bondurant David W.
Mobley Kenneth J.
Peters Michael
Enhanced Memory Systems Inc.
Kubida, Esq. William J.
Lembke, Esq. Kent
Meza, Esq. Peter J.
Nguyen Than
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