Double data rate scheme for data output

Details Double data rate scheme for data output Double data rate scheme for data output

2007-07-31

2007-07-31

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S105000, C711S157000, C711S167000, C710S020000, C710S021000, C710S060000, C710S007000, C365S189020, C365S189050, C365S233100

Reexamination Certificate

active

11380617

ABSTRACT:
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

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