Double data rate scheme for data output

Details Double data rate scheme for data output Double data rate scheme for data output

2006-08-15

2006-08-15

Verbrugge, Kevin (Department: 2198)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S105000, C711S157000, C711S167000, C710S020000, C710S021000, C710S060000, C710S007000, C365S189020, C365S189050, C365S233100

Reexamination Certificate

active

07093095

ABSTRACT:
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

REFERENCES:
patent: 4463443 (1984-07-01), Frankel et al.
patent: 5007012 (1991-04-01), Dujari
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5506814 (1996-04-01), Hush et al.
patent: 5592488 (1997-01-01), Thomann et al.
patent: 5657289 (1997-08-01), Hush et al.
patent: 5699314 (1997-12-01), Hush et al.
patent: 5703826 (1997-12-01), Hush et al.
patent: 5717647 (1998-02-01), Hush et al.
patent: 5778007 (1998-07-01), Thomann et al.
patent: 5815447 (1998-09-01), Thomann
patent: 5822266 (1998-10-01), Kikinis
patent: 5834813 (1998-11-01), Ma et al.
patent: 5854800 (1998-12-01), Thomann et al.
patent: 5875134 (1999-02-01), Cloud
patent: 5915128 (1999-06-01), Bauman et al.
patent: 5920511 (1999-07-01), Lee et al.
patent: 5923901 (1999-07-01), Kawaura
patent: 5953258 (1999-09-01), Thomann
patent: 5963469 (1999-10-01), Forbes
patent: 5986948 (1999-11-01), Cloud
patent: 6011751 (2000-01-01), Hirabayashi
patent: 6060916 (2000-05-01), Park
patent: 6067585 (2000-05-01), Hoang
patent: 6078546 (2000-06-01), Lee
patent: 6084802 (2000-07-01), Shinozaki
patent: 6094375 (2000-07-01), Lee
patent: 6112267 (2000-08-01), McCormack et al.
patent: 6118729 (2000-09-01), Hirabayashi et al.
patent: 6151271 (2000-11-01), Lee
patent: 6282128 (2001-08-01), Lee
patent: 6314042 (2001-11-01), Tomishima et al.
patent: 6446180 (2002-09-01), Li et al.
patent: 6477107 (2002-11-01), Lee
patent: 6477592 (2002-11-01), Chen et al.
patent: 6516363 (2003-02-01), Porter et al.
patent: 6522599 (2003-02-01), Ooishi et al.
patent: 6694416 (2004-02-01), Thomann et al.
patent: 6823407 (2004-11-01), Porter et al.
patent: 19821641 (1999-07-01), None
patent: 19821641 (1999-07-01), None
patent: 0778575 (1997-06-01), None
patent: 11-066847 (1999-03-01), None
patent: 11-191292 (1999-07-01), None
patent: 11-195296 (1999-07-01), None
patent: 11-213668 (1999-08-01), None
patent: WO-99/50852 (1999-10-01), None
“Increasing Data Read Rate from Memories”,IBM Technical Disclosure Bulletin, 30, (May, 1988),339-341.
“Japanese Office Action from corresponding Japanese Application No. 2001-520417”, (2005), 5 pages.

Affiliated with

Also associated with

Rating

Double data rate scheme for data output does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Double data rate scheme for data output, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double data rate scheme for data output will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3672261