Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2003-02-04
2004-09-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189020
Reexamination Certificate
active
06791889
ABSTRACT:
As manufacturers introduce computers with faster and more powerful CPUs, there remains a struggle within the memory industry to develop semiconductor technology that allows system memory to exchange data with today's high performance CPUs more quickly and efficiently. One semiconductor technology called Synchronous Dynamic Random Access Memory or more commonly, Synchronous DRAM or SDRAM was designed to match system memory speed with that of the processor. SDRAM was designed to improve the performance of the overall computer because the memory is fast and utilizes a clock that is synchronized with the processor. Therefore, the processor may perform other operations without waiting for the memory to locate the address and read or write the data.
Double Data Rate-Synchronous DRAM, a type of SDRAM that supports data transfers on both the rising and falling clock edges of each clock cycle, effectively doubles the memory chip's data throughput. However, synchronizing the data from the SDRAM to a system clock provided by the processor necessitates precise timing circuitry that is power consuming. Accordingly, there is a continuing need for better ways to provide flexibility for transferring data between a microprocessor and memory while preserving low power operation and the stability of the data transfers.
REFERENCES:
patent: 6091664 (2000-07-01), Ramanadin
patent: 6134180 (2000-10-01), Kim et al.
patent: 6282132 (2001-08-01), Brown et al.
Hoang Huan
Intel Corporation
Parker Lanny L.
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