Double data rate dynamic logic

Details Double data rate dynamic logic Double data rate dynamic logic

2001-05-09

2002-08-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S096000, C326S097000, C327S208000, C327S214000, C327S224000

Reexamination Certificate

active

06441648

ABSTRACT:

FIELD
Embodiments of the present invention are directed to digital circuits, and more particularly, to dynamic logic gates.
BACKGROUND
Dynamic (or domino) logic gates are ubiquitous building blocks in many high performance digital circuits. In particular, for microprocessors, dynamic logic gates find their way into many functional units, such as multipliers and adders, among others. Dynamic logic gates allow for pipelining to increase throughput, and make use of nMOSFETs (Metal Oxide Semiconductor Field Effect Transistor) to speed logic evaluation.
An example of a four stage dynamic logic circuit (or domino circuit) is provided in FIG.
1
. Each nMOSFET logic unit
101
,
102
,
103
, and
104
denotes one or more nMOSFETs connected in various combinations of parallel and serial configurations so as to achieve the overall desired Boolean expression performed by the dynamic logic circuit. For simplicity, only one input port is shown for each nMOSFET logic unit, but there may in fact be several such input ports for each nMOSFET logic unit. Four clock signals, &phgr;
i
=1, 2, 3, 4, are provided in FIG.
1
. These clock signals are staggered in phase by &pgr;/2, that is, for each i=1, 2, 3, &phgr;
i+1
lags &phgr;
i
by &pgr;/2 radians.
Considering stage
1
of the dynamic logic circuit of
FIG. 1
, the pre-charge phase begins on the falling edge of the clock signal &phgr;
1
, i.e., when &phgr;
1
transitions from HIGH to LOW, so that pMOSFET
106
turns ON and nMOSFET
108
turns OFF. With nMOSFET
108
OFF, nMOSFET logic unit
101
is isolated from ground (substrate), and with pMOSFET
106
ON, node
110
is pulled HIGH. Inverter
112
and pMOSFET
114
function as a keeper, so that node
110
is weakly held HIGH unless otherwise pulled LOW by nMOSFET logic unit
101
during the evaluation phase. Inverter
116
is a static inverter, so that the input to stage
2
of the dynamic logic circuit is LOW when stage
1
is in its pre-charge phase. The evaluation phase begins on the rising edge of the clock signal &phgr;
1
, i.e., when &phgr;
1
transitions from LOW to HIGH, so that nMOSFET logic unit
101
is now coupled to ground via nMOSFET
108
. In the evaluation phase, nMOSFET logic unit
101
may pull node
110
LOW depending upon its input. If not, then keeper pMOSFET
114
keeps node
110
HIGH as mentioned earlier.
By staggering the phases of the clock signals, the various stages illustrated in
FIG. 1
may be pipelined together to achieve a high throughput, so that input is provide, to the dynamic logic circuit at the clock rate.


REFERENCES:
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5272397 (1993-12-01), Chen et al.
patent: 5384493 (1995-01-01), Furuki
patent: 6090153 (2000-07-01), Chen et al.
patent: 6265899 (2001-07-01), Abdel-Hafeez et al.

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