Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2011-08-02
2011-08-02
Nguyen, Khai M (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C377S052000, C377S111000, C377S116000
Reexamination Certificate
active
07990304
ABSTRACT:
In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
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Yoshihara, Satoshi, et al., “A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change,” IEEE Journal of Solid-State Circuits, vol. 41, No. 12, Dec. 2006, pp. 2998-3006.
Kim Kyung-min
Koh Kyoung-Min
Lim Yong
Mills & Onello LLP
Nguyen Khai M
Samsung Electronics Co,. Ltd.
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