Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2006-06-27
2010-06-15
Connolly, Mark (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C365S233130
Reexamination Certificate
active
07739538
ABSTRACT:
A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
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Berry Christopher J.
Chen Jonathan Y.
Fee Michael
Meaney Patrick J.
Wagstaff Alan P.
Connolly Mark
Fleit Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
International Business Machines - Corporation
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