Double buffering operations between the memory bus and the expan

Details Double buffering operations between the memory bus and the expan Double buffering operations between the memory bus and the expan

1997-07-31

1999-02-09

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395310, 395306, 395872, 711100, 711143, G06F 1316, G06F 1320

Patent

active

058705686

ABSTRACT:
Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

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Intel Corp., 1993 Peripheral Components, pp. 1-104 to 1-128, 1993.
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