Double buffering of serial transfers

Details Double buffering of serial transfers Double buffering of serial transfers

2007-07-17

2007-07-17

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C714S005110, C710S003000, C710S052000

Reexamination Certificate

active

10775614

ABSTRACT:
Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register, and the data bits are serially shifted into a data shift register. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.

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