Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-10-24
2006-10-24
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S005000, C711S103000, C711S148000, C711S149000
Reexamination Certificate
active
07127564
ABSTRACT:
A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.
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Noviello Donald D.
Schoepflin Robert W.
Streiber Ronald W.
Virzi John D.
Wahler Richard E.
Henrichs Russell E.
Hood Jeffrey C.
Kim Matthew
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Hetul
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