Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-03
2003-11-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06653692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a mask read-only memory (to be abbreviated as ROM hereafter) array structure and, more particular, to a mask ROM array structure employing a double access path to access the data simultaneously so as to achieve high reliability and high-speed operation.
2. Description of the Prior Art
In recent years, due to the increasing need for the performances in terms of speed, size, power consumption and ease of fabrication of electronic products, the electronics industry has made a lot of efforts on semiconductor processing techniques for downsized and highly integrated devices on the one hand. On the other hand, concerning IC design, there has been provided with new layout approaches in accordance with the state-of-the-art processing techniques so as to obtain an overall improvement in reliability as well as in operation speed.
Many prior arts have been disclosed, such as the U.S. Pat. No. 5,117,389 entitled “Flat-cell read-only memory integrated circuit” filed by Yiu et al (Macronix International Co., Ltd., Taiwan) and the U.S. Pat. No. 6,084,794 entitled “High speed Flat-cell mask ROM structure with select lines” filed by Lu et al (Winbond Electronics.Corp., Ltd., Taiwan.) The performance of a ROM is easily affected by the access path during data access since the equivalent resistance and the parasitical capacitance in the conductive path depend on the access path.
Please refer to
FIG. 1
, which is a schematic circuit diagram in accordance with the U.S. Pat. No. 5,117,389. Within this circuit design architecture, for example, when a data in the cell array is to be accessed, it can be chosen either by the bank left select transistor SBL
N
or the bank right select transistor SBR
N
. Then through the block select transistors M
1
and M
2
and the contact holes
100
-
1
and
100
-
2
, a conductive path is formed from the virtual ground VG
N
to the metal data line BL
N
. Thereafter, the value 1 or 0 stored in the memory cell C is accessed via the metal data line BL
N
by the sense amplifier. The conductive path can expressed as:
VG
N
→
100
-
1
→M
1
→L
2
→C→M
2
→
100
-
2
→BL
N
Please refer to
FIG. 2
, which is a schematic circuit diagram in accordance with the U.S. Pat. No. 6,084,794. Within this circuit design architecture, for example, when the data in the cell array is to be accessed, one of even memory cell C
00
or odd memory cell C
01
is chosen by the even select line ESi or the odd select line Osi respectively. Then through the block select transistors B
0
and B
1
and the contact holes (not shown), a conductive path is formed from the metal bit line BL
i−1
to the metal bit line BL
i
. Thereafter, the stored value 1 or 0 is accessed via the metal bit line BL
i
by the sense amplifier. For example, when the data stored in the even memory cell C
00
is to be accessed, the conductive path can expressed as:
BL
i−1
→B
0
→C
00
→E
1
→BL
i
Accordingly, the resistance in the conductive path in a flat-cell ROM is relatively large. When 0 is to be accessed, the current will be suppressed and a large voltage drop occurs across the n
+
-buried region due to large resistance. Since the large voltage drop across the n
+
-buried region reduces the pull low margin of the sense amplifier, the operation condition becomes critical. On the other hand, the suppressed current prolongs the pull low time for accessing 0 and thus decreases the operation speed.
Therefore, there is need for providing a novel circuit architecture design that can effectively improve the reliability and the operation speed.
SUMMARY OF THE INVENTION
It is the primary object of the present invention to provide a double access path mask ROM array structure employing a double access path to access the data simultaneously so as to improve high reliability operation.
It is another object of the present invention to provide a double access path mask ROM array structure employing a double access path such that the operation speed when accessing 0 is enhanced since the equivalent resistance is the parallel resistance of the independent conductive paths.
In order to achieve the foregoing objects, the present invention provides a double access path mask ROM array structure, comprising a plurality of pairs of banks, wherein said each pair of bank comprises: a plurality of n
+
-buried regions formed on a substrate to function as part of a first access path and part of a second access path; an insulating layer of substantially constant thickness formed on said substrate; a plurality of contact holes penetrating said insulating layer, wherein two of said contact holes construct a conductive path to the ground and another two of said contact holes construct a conductive path to an external sense amplifier; a plurality of block select transistors; a plurality of select cell transistors; a plurality of conductive bit lines, connecting the sources of said different block select transistors to said respective contact holes; a plurality of word lines; a cell array composed of said plurality of word lines to store data; and, a first metal line and a second metal line, forming part of a double access path.
Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 5117389 (1992-05-01), Yiu
patent: 5453392 (1995-09-01), Hong et al.
patent: 5631481 (1997-05-01), Hsue et al.
patent: 5892713 (1999-04-01), Jyouno et al.
patent: 6084794 (2000-07-01), Lu et al.
patent: 6150700 (2000-11-01), Lee
Holtek Semiconductor Inc.
Nelms David
Tran Long
Troxell Law Office PLLC
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