Doping control in selective area growth (SAG) of InP epitaxy...

Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor

Reexamination Certificate

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C117S105000, C438S045000

Reexamination Certificate

active

06245144

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of making semiconductor devices and, more particularly, to a method of forming epitaxial layers using a metalorganic chemical vapor deposition (MOCVD) process.
2. Description of the Related Art
One of the most significant developments in semiconductor technology in recent years has been the increased use of III-V materials such as gallium arsenide and indium phosphide, and their ternary and quaternary alloys such as indium-gallium-arsenide-phosphide, as the active materials of semiconductor devices. The band gap characteristics of such materials typically make them candidates for optoelectronic and photonic applications such as lasers, light emitting diodes and photodetectors. For integrated circuit use, their high electron mobility often makes them preferable to the more commonly used semiconductor, silicon. Fabrication of such devices generally requires epitaxal growth of one or more layers on a single-crystal substrate. Epitaxial growth refers to a method of depositing a material on a substrate such that the crystal structure of the deposited material effectively constitutes an extension of the crystal structure of the substrate.
The three broad classes of methods for deposition by epitaxial growth are liquid phase epitaxy, vapor phase epitaxy and molecular beam epitaxy which respectively involve deposition from a liquid source, a vapor source and a molecular beam. A particularly promising form of vapor phase epitaxy is a method for deposition from a gas including a metalorganic compound; this process, known as metalorganic chemical vapor deposition (MOCVD), is described in a number of scientific publications including, “Metalorganic Chemical Vapor Deposition of III-V Semiconductor,” M. J. Ludowise, Journal of Applied Physics, Vol. 58, No. 8, Oct. 15, 1985, pp. R31-R55, and the paper, “Metalorganic Chemical Vapor Deposition,” P. Daniel Dapkus, American Review of Material Sciences, Annual Reviews, Inc., 1982, pp. 243-268, both of which are expressly incorporated by reference herein. MOCVD processes make use of a reactor in which a heated substrate is exposed to a gaseous metalorganic compound containing one element of the epitaxial layer to be grown and a gaseous second compound containing another element of the desired epitaxial material. For example, to grow the III-V material gallium arsenide, one may use the metalorganic gas triethylgallium [(C
2
H
5
)
3
Ga] as the gallium source and arsine (AsH
3
) as the source of the group V component, arsenic. The gas mixture is typically injected axially at the top of a vertically extending reactor in which the substrate is mounted on a susceptor that is heated by a radio-frequency coil. The gases are exhausted from a tube at the end of the reactor opposite the input end.
Recently, the use of selective area growth (SAG) in the manufacture of optoelectronic components has increased chip functionality by increasing the integration of more components on a single device (e.g. beam expanded laser, electromodulated lasers). Silane (SiH
4
) is a typical n-type precursor gas used in low pressure metalorganic chemical vapor deposition (LPMOCVD) technology. With the use of silane, the silicon dopant concentration in the SAG area is always less than the adjacent field area (i.e., the region outside the SAG area). This relative difference in dopant concentration is often referred to as the silicon reduction ratio (SRR). In order to optimize device performance, it is desirable to maintain substantially the same silicon dopant levels in and out of the SAG areas, i.e., a silicon reduction ratio of 1.
Accordingly, there is a need for a low-cost technique to adjust the silicon reduction ratio in the MOCVD process.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method to vary the ratio of silicon dopant in a SAG area and an adjacent maskless area so as to optimize the performance of integrated optoelectonic devices.
According to an aspect of the invention, the ratio of silicon in a masked area to an unmasked area can be modulated between about 0.6 and 1.3 by varying the growth conditions inside a MOCVD reactor chamber.
Advantageously, the present invention employs growth conditions in the reactor such that the silicon reduction ratio is approximately 1.
In one embodiment, the invention provides a method of controlling the relative amounts of silicon dopant inside and outside of enhanced growth regions on an indium phosphide substrate using a metalorganic chemical vapor deposition (MOCVD) process. The inventive method includes the steps of positioning the indium phosphide substrate in a reactor chamber, and defining an enhanced growth region on the substrate by depositing a dielectric mask on the substrate. The indium phosphide substrate is heated to a growth temperature of between about 600 and 630° C. The pressure in the reactor chamber is adjusted to between about 40 and 80 Torr. A first gas containing a metalorganic compound comprising indium and a hydrogen carrier gas, and a second gas containing a hydride (e.g., phosphide) and a doping gas containing SiH
4
are introduced into the reactor chamber. The first gas and the second gas are mixed and forced over the substrate in a laminar flow such that the mixed convection parameter is between about 0.31 and 0.33. An n-type indium phosphide epitaxial layer is thereby grown over the substrate by reacting the first gas with the second gas and thermally decomposing the doping gas, whereby areas inside and outside of the growth enhanced region contain substantially the same amount of silicon dopant.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.


REFERENCES:
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patent: 5061643 (1991-10-01), Yagi
patent: 5186756 (1993-02-01), Benko et al.
patent: 5585309 (1996-12-01), Mori et al.
patent: 5723360 (1998-03-01), Iwasaki
patent: 5728215 (1998-03-01), Itagaki et al.
patent: 6066204 (2000-05-01), Haven

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