Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-05-15
2007-05-15
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S097000, C326S098000
Reexamination Certificate
active
10608421
ABSTRACT:
A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.
REFERENCES:
patent: 6204696 (2001-03-01), Krishnamurthy et al.
patent: 6346831 (2002-02-01), Krishnamurthy et al.
V. Kursun and E. G. Friedman, “Domino Logic with Variable Threshold Voltage Keeper,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in press).
V. Kursun and E. G. Friedman, “Variable Threshold Voltage Keeper for Contention Reduction in Dynamic Circuits,” Proceedings of the IEEE International ASIC/SOC Conference, pp. 314-318, Sep. 2002.
V. Kursun and E. G. Friedman, “Domino Logic with Dynamic Body Biased Keeper,” Proceedings of the European Solid-State Circuits Conference, pp. 675-678, Sep. 2002.
Friedman Eby G.
Kursun Volkan
Blank Rome LLP
Tran Anh Q.
University of Rochester
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