Domino logic with self-timed precharge

Details Domino logic with self-timed precharge Domino logic with self-timed precharge

2001-01-25

2002-07-16

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S098000, C326S121000

Reexamination Certificate

active

06420904

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of electronic circuit design, and in particular to the design of logic circuits for use in a domino-chain of logic devices.
2. Description of Related Art
The use of domino logic is well known in the art. As the name implies, a domino logic circuit propagates logic values from one stage to the next; a first stage propagates a logic result to a second stage, which propagates the result to a third stage, and so on. Typically, a clock signal is used to preset all of the stages during a first phase of the clock, and to enable the stages to change state in a second phase of the clock, depending upon the input signals and logic function of each stage. Each stage is configured to provide an inactive state when it is precharged, such that this stage can have no effect on the next stage while it is in the inactive state. The state remains inactive until the stage is enabled and the application of the input to the gate's logic function results in a change of state to an active state; only then will the next stage potentially change state, depending upon the application of this active state to the next stage's logic function.
FIG. 1
illustrates an example domino CMOS circuit
100
comprising a series of domino stages
110
a-c.
In this example, each stage includes a P-channel transistor
120
p
and an N-channel transistor
120
n
in series with its logic function
130
a-c,
each transistor
120
p,
120
n
being gated by a common clock, or precharge, signal
141
, such that only one of the transistors is conducting at any time, thereby precluding the flow of DC current, for low power consumption. Both transistors
120
p
and
120
n
are required, to prevent the flow of DC current when the precharge transistor
120
p
conducts and the logic function
130
also conducts.
The logic function
130
may be any combination of transistors, but generally includes transistors of one type, either p-channel or n-channel. Because n-channel devices are generally faster than p-channel devices of equal size, the logic function
130
in high-speed designs generally include only n-channel devices. Logic function
130
b
is illustrated as a two-input OR gate, implemented as a NOR combination of n-channel devices
131
,
132
, and an inverter
135
. In this example, the clock is structured to precharge the logic function
130
via the p-channel device when it is at a logic-0 level, and to ‘evaluate’ the logic function when it is at the logic-1 level.
In this n-channel logic example, when the clock is in the precharge state (logic-0), the transistors
120
p
conduct, and the output of each logic function
130
provides a logic-0 output, via, for example, a corresponding inverter
135
in each logic function
130
. Because the logic function
130
includes only n-channel devices, the logic-0 output from one stage cannot alter the logic state of a subsequent stage. To avoid noise-induced transients, a weak-latch (not shown) is often used to hold the output at a logic-0 state until it is actively driven to a logic- I state by a discharge through the n-channel devices.
When the clock transitions to the evaluate state (logic-1), the p-channel transistors
120
p
cease conduction, and the n-channel devices
120
n
conduct, allowing the logic function
130
to change from the precharge state, as determined by its input state. Note that, in an n-channel logic function
130
, a transition to the active, non-precharge, state cannot occur unless an input transitions to a logic-1 state. That is, changes in state propagate sequentially through the stages
110
a
-
110
b
-
110
c,
in a falling-domino-like manner.
As would be evident to one of ordinary skill in the art, if a logic function
130
includes only p-channel devices, the n-channel transistor
120
n
would be used to provide a ‘precharge’ to logic-0, and the preceding stage would be configured to provide a logic-1 state as the precharge state. Alternating n-channel and p-channel stages may be employed to eliminate the need for the inverter
135
in each logic function
130
. Other configurations, including p-channel and n-channel devices within a logic function
130
(with appropriate precharge states on each input) are also feasible.
The speed of a domino stage is determined by the delay of the logic function, plus the delay through the evaluation transistor,
120
p
or
120
n
. Generally, the logic functions
130
in a typical design, such as an adder or multiplier, include only two or three inputs, and thereby a maximum stack size of two or three transistors in series. Assuming equally sized transistors, the evaluation transistor
120
can amount to a third or a quarter of the propagation delay of each stage. A large size evaluation transistor will reduce the delay through the transistor, but at the cost of circuit area, and increased loading on the clock circuit (and thereby increased switching power consumption).
BRIEF SUMMARY OF THE INVENTION
It is an object of this invention to eliminate the delay caused by the use of an evaluation transistor in a pre-charged logic stage. It is a further object of this invention to reduce the circuit area required in a pre-charged logic stage. It is a further object of this invention to reduce the load of a clock circuit in a pre-charged logic design. It is a further object of this invention to reduce the power consumption of a pre-charged logic design.
These objects and others are achieved by controlling the precharge of a logic stage based on the precharge delay of a prior logic stage. The precharge of the logic stage does not occur until the output of the prior logic stage corresponds to the precharge logic state. Because the precharge logic state output of a preceding stage is an inactive state of a subsequent logic stage, the logic function of the subsequent logic stage is in a non-conducting state when the output of the prior logic stage is in the precharge logic state. By providing the precharge to a subsequent stage only after the output of the prior stage is in the precharge state, there can be no DC current flow during the precharge of the subsequent stage, and the need for an evaluation transistor to block the DC current flow during precharge is eliminated. The elimination of the evaluation transistor eliminates the delay introduced by the evaluation transistor in a precharge logic age, reduces the circuit area for the logic stage, reduces the load on the clock circuit, and reduces the power consumption of each logic stage.


REFERENCES:
patent: 5671151 (1997-09-01), Williams
patent: 6040716 (2000-03-01), Bosshart
patent: 6239612 (2001-05-01), Milshtein et al.
patent: WO-98/29949 (1998-07-01), None

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