Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-12-06
2002-11-26
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000
Reexamination Certificate
active
06486706
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor logic devices, and more specifically to domino logic circuitry having a novel NMOS output pull-up.
BACKGROUND OF THE INVENTION
Semiconductor operational frequencies are ever increasing, requiring circuitry and processes that support these faster clock rates. Domino circuits have been used in such circuits to speed processing, due to the way in which a domino logic circuit handles data. A typical domino logic circuit receives data on a first transition of a clock, and couples a logically derived signal to external circuitry on a next transition of the clock.
A conventional domino circuit includes dynamic circuitry coupled to static gate circuitry. The dynamic circuitry pre-charges an input of the static circuitry when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry often is n-type metal oxide semiconductor (NMOS) pull-down circuitry, that is operable to pull down the level of a relatively weakly held pre-charged circuit node. The node is then latched in static CMOS circuitry to provide a stable output until the next logical cycle.
But, the speed of such logic is limited by the time it takes to pre-charge the dynamic circuit node that provides the data signal to the static CMOS latch and the output, and by the time it takes to pull down the weakly-held precharged node voltage to provide a low signal level to the static CMOS latch circuitry and to change the state of the output
One solution to such problems is to reduce the physical size of the circuit elements and reduce the supply and threshold voltages within the circuit, resulting in physically smaller devices able to change state over a smaller voltage range more quickly. But, the reduced threshold voltages and smaller geometry result in high subthreshold and leakage current in the transistors. Also, the low threshold voltages coupled with faster signal edges and greater noise coupling due to smaller geometry contribute to increasingly substantial noise problems. A higher threshold voltage may be used to compensate for higher noise, but a circuit providing a lower threshold voltage with faster operation is desirable.
For these reasons and others that will be apparent to those skilled in the art upon reading and understanding this specification, a need exists for a domino logic circuit that retains a low threshold voltage while providing an adequate noise margin.
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De Vivek K.
Narendra Siva G.
Ye Yibin
Cho James H
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tokar Michael
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