Domino logic family

Details Domino logic family Domino logic family

2000-03-07

2002-03-26

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S098000, C326S112000

Reexamination Certificate

active

06362659

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to digital logic families, and more particularly, to domino logic families for high speed circuits.
In general, the term “domino logic” is used to refer to an arrangement of logic circuit stages that may, for example, be cascaded together in an integrated circuit array configuration. A signal may be input to a first stage where it is evaluated in order to provide an output signal to a second stage where that output signal is again evaluated to provide an output signal for propagation to and evaluation by yet another stage in the circuit. Thus, a “domino” effect is achieved whereby signals are sequentially propagated through an array of “stages” or “domino blocks”, and each successive stage performs an evaluation of an input condition until a final output is provided at a final output stage.
Domino logic circuits may be arranged so that signals can propagate through the various stages without being separately clocked at each stage. Accordingly, a domino arrangement allows a signal to be processed through a relatively complex logic function during a single clock cycle. This ability of a domino circuit obviates the need for plural clock cycles to process the input signals, and also decreases the overall processing time of the logic function. Conventional domino logic circuits are discussed in “High-Speed Compact Circuits with CMOS”, Krambeck et al., IEEE
Journal of Solid-State Circuits,
Vol. SC-17, No. 3, June 1982, pp. 614-619, and “High-Speed CMOS Design Styles”, Kluwer Academic Publishers, Boston, 1998, pp. 93-98.
A conventional domino logic OR gate is shown in FIG.
1
. The OR gate includes PMOS transistors
10
,
12
, and
14
, NMOS transistors
16
and
18
, and logic block
20
. PMOS transistor
12
and NMOS transistor
16
are arranged to form a conventional CMOS inverter having an input
22
and an output
24
. The input
22
corresponds to an internal or evaluation node within the circuit. The gate of PMOS transistor
14
is coupled to the output
24
of the inverter. The source of PMOS transistor
14
is coupled to VDD
26
, and the drain of the PMOS transistor
14
is coupled to the evaluation node
22
. PMOS transistor
14
is used to latch in the internal node just after the pre-charge phase.
The gate NMOS transistor
18
is coupled to the clock input “C”
30
, and the source of NMOS transistor
18
is coupled to ground. Logic block
20
is arranged between the evaluation node
22
and the drain of NMOS transistor
18
. For an OR gate, the logic block
20
may include NMOS transistor
32
and NMOS transistor
34
, arranged in a parallel configuration. The gate of NMOS transistor
32
is coupled to a first input signal “A”, and the gate of NMOS transistor
34
is coupled to a second input signal “B”. The drains of both NMOS transistor
32
and NMOS transistor
34
are coupled to the evaluation node
22
, and the sources of both NMOS transistor
32
and NMOS transistor
34
are coupled to the drain of NMOS transistor
18
, as shown.
Finally, the gate of PMOS transistor
10
is coupled to the clock input “C”. The source of PMOS transistor
10
is coupled to VDD
26
, and the drain of PMOS transistor
10
is coupled to the evaluation node
22
.
During operation, when the clock input “C” is low, PMOS transistor
10
pre-charges the evaluation node
22
. This causes the output
24
of the inverter to go low. Because “C” is low, NMOS transistor
18
is off, which effectively disconnects the logic block
20
from ground. Accordingly, the evaluation node
22
is pre-charged high, with the output
24
of the inverter low.
When the clock input “C” goes high, the circuit enters an “evaluate” phase where the desired logic function is performed. When “C” goes high, PMOS transistor
10
turns off, and NMOS transistor
18
turns on. Because NMOS transistor
18
is on, the source terminals of NMOS transistors
32
and
34
are effectively grounded through NMOS transistor
18
. If either “A” or “B” are high, the evaluation node
22
is coupled to ground through either NMOS transistor
32
or NMOS transistor
34
, and NMOS transistor
18
. Thus, the evaluation node
22
is pulled low if either “A” or “B” (or both) are high. When the evaluation node
22
is pulled low, the output
24
of the inverter goes high. This turns off PMOS transistor
14
. Other functions can be provided by changing the arrangement of the NMOS transistors in logic block
20
. For example, an AND gate may be provided by including two NMOS transistors in series, rather than in parallel.
A limitation of conventional domino logic circuits is that significant performance inhibitors often exist. For example and referring to
FIG. 1
, the placement of NMOS transistor
18
in series with the logic transistors
32
and
34
tends to increase the resistance of the path from the evaluation node, through the logic block, and to ground. Accordingly, NMOS transistor
18
may increase the time required to discharge the evaluation node
22
during the evaluation phase.
In addition, PMOS transistor
10
may be required to properly pre-charge the evaluation node
22
during a pre-charge phase. PMOS transistor
10
can add significant capacitance to the evaluation node
22
, and thus may also increase the time required to discharge the evaluation node
22
during the evaluation phase.
Finally, NMOS transistor
16
, which is part of the inverter, typically must be relatively large to provide a reasonably short pre-charge time. However, the gate capacitance of NMOS transistor
16
can add significant capacitance to the evaluation node
22
. As indicated above, this can significantly increase the time required to discharge the evaluation node
22
during the evaluation phase. Each of these performance inhibitors reduce the performance of the circuit. What would be desirable, therefore, is a domino logic circuit and circuit family that has reduced capacitance on the evaluation node for increased circuit performance.
SUMMARY OF THE INVENTION
The present invention provides a domino logic circuit and circuit family that has reduced capacitance on an evaluation node for increased circuit performance. This is preferably accomplished by removing one or both of the clocked transistors of a conventional domino logic circuit (e.g., transistors
10
and
18
of FIG.
1
), and providing a single clocked transistor that controls the logic state of the output of the inverter. It has been found that this may: (1) reduce or eliminate the series resistance in line with the logic block; (2) reduce or eliminate the capacitance contributed by the clocked pre-charge transistor (e.g., transistor
10
of
FIG. 1
) to the evaluation node; and (3) reduce the size and thus the capacitance contributed by one of the transistors of the inverter to the evaluation node of the circuit. Each of these may increase the performance of the circuit.
In an illustrative embodiment, a domino logic circuit is provided that includes an inverter, a pre-charge transistor, a logic block, and a pre-charge control transistor. The inverter has an input and an output. Like prior art domino logic circuits, the input of the inverter corresponds to the evaluation node of the domino logic circuit. The pre-charge transistor is coupled to the evaluation node of the domino logic circuit, and is controlled by the output of the inverter. That is, the pre-charge transistor may pre-charge the evaluation node when the output of the inverter is in a predetermined pre-charged state. The pre-charge control transistor selectively pulls the output of the inverter to the pre-charged state, when enabled. The pre-charge control transistor is preferably controlled by a clock signal having a pre-charge phase and an evaluation phase.
The logic block is coupled to the evaluation node, and conditionally discharges the evaluation node during the evaluation phase. The logic block is preferably coupled directly between the evaluation node and a power supply terminal, such as VDD or ground. Accordingly, there is little or no resistance in s

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