Domino logic element realizing high speed dynamic logic circuit

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

Reexamination Certificate

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Details

C326S098000, C326S093000

Reexamination Certificate

active

06320420

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a domino logic element and a dynamic logic circuit, and more particularly to a domino logic element and a dynamic logic circuit using such domino logic elements which is not affected by a clock skew and is capable of operating at high speed.
BACKGROUND OF THE INVENTION
A dynamic logic circuit is known as one of means for realizing semiconductor logic circuits. Dynamic logic circuit has the merits of high operating speed, small power consumption, small layout area in an integrated circuit, and the like. Especially, a domino logic circuit as a kind of the dynamic logic circuit is widely used to realize an integrated circuit which should have a high operating speed.
FIG. 10
is a circuit diagram showing a structure of a conventional domino logic element
400
used for constituting a domino logic circuit. As shown in
FIG. 10
, the conventional domino logic element
400
comprises a p-type MOS transistor
401
for precharging, an n-type MOS transistor
402
for discharging, an n-type MOS transistor logic network (hereafter referred to as an nMOS logic network)
403
, and an output inverter
404
.
The source terminal of the p-type MOS transistor
401
is coupled to a power supply terminal VDD, the gate terminal thereof is coupled to a clock input terminal
410
, and the drain terminal thereof is coupled to a dynamic node
406
. The p-type MOS transistor
401
functions to precharge the dynamic node
406
, based on a clock signal&phgr; inputted from the clock input terminal
410
.
The nMOS logic network
403
comprises a plurality of n-type MOS transistors
403
a
whose gate terminals are coupled to signal input terminals
420
. The n MOS logic network
403
are disposed between the dynamic node
406
and the n-type MOS transistor for discharging
402
, namely, are coupled between the dynamic node
406
and the drain terminal of the n-type MOS transistor for discharge
402
. Depending on the connection of the n-type MOS transistor
403
a
in the nMOS logic network
403
, the domino logic element
400
performs a desired logical function.
The drain terminal of the n-type MOS transistor
402
for discharging is coupled to the nMOS logic network
403
, the gate terminal thereof is coupled to the clock input terminal
410
, and the source terminal thereof is coupled to the ground terminal GND. The n-type MOS transistor
402
, together with the nMOS logic network
403
, function to discharge electric charges stored in the dynamic node
406
, based on the clock signal &phgr; inputted from the clock input terminal
410
.
The output inverter
404
inverts a logical potential of the dynamic node
406
, and outputs an inverted logical potential to an output terminal
405
.
Conventionally, the operation of the domino logic element
400
takes place in two distinct phases (or periods), i.e, a precharge phase (or period) and an evaluation phase (or period). These phases are alternately repeated.
In a precharge phase, a potential of the clock signal &phgr; supplied from the clock input terminal
410
is a LOW potential level (hereafter referred to as L level) which is equal to the ground potential level at the ground terminal GND. In this case, the p-type MOS transistor
401
is turned on, that is, the source terminal and the drain terminal thereof are electrically coupled to each other. On the other hand, the n-type MOS transistor
402
is turned off, that is, the source terminal and the drain terminal thereof are isolated from each other. Therefore, a precharge operation is performed in which electric charges are stored into the dynamic node
406
until the potential of the dynamic node
406
becomes a HIGH potential level (hereafter referred to as H level) that is equal to the potential of the power supply terminal VDD.
In an evaluation phase, a potential of the clock signal &phgr; supplied from the clock input terminal
410
is H level. In this case, the p-type MOS transistor
401
is turned off, and the n-type MOS transistor
402
is turned on. The nMOS logic network
403
couples or isolates between the dynamic node
406
and the drain terminal of the n-type MOS transistor
402
, depending on logical values of input signals at the signal input terminals
420
. Therefore, at the evaluation phase, electric charges of the dynamic node
406
which are precharged during the precharge phase are selectively discharged or retained depending on the logical values of the input signals at the signal input terminal
420
. Thereby, an output signal is obtained from the output terminal
405
, which output signal has a logical value obtained by performing a logical operation by the nMOS logic network
403
on the input signals at the input terminals
420
.
Usually, since a circuit scale of the nMOS logic network
403
is limited by a circuit area and the like, a domino logic circuit is formed by connecting a plurality of domino logic elements
400
in tandem, to realize a desired logic circuit. Here, in order to make it possible to dispose as many logic elements as possible in one cycle of a clock signal, in most instances, a plurality of domino logic circuits are used having different timings of precharge and evaluation phases.
FIG. 11
is a circuit diagram showing an example of a logic circuit realized by using domino logic circuits controlled by two phase clock signals &phgr;
1
and &phgr;
2
. The logic circuit shown in
FIG. 11
comprises domino logic circuits
510
and
520
each of which is constituted of a plurality of tandem connected domino logic elements
400
, and latch circuits
530
,
540
and
550
. In the logic circuit shown in
FIG. 11
, domino logic circuit
510
, the latch circuit
540
, the domino logic circuit
520
and the latch circuit
550
operate in one cycle of a clock signal.
The two phase clock signals &phgr;
1
and &phgr;
2
have a relationship complementary to each other. When the clock signal &phgr;
1
has H level, the clock signal &phgr;
2
has L level, and when the clock signal &phgr;
1
has L level, the clock signal &phgr;
2
has H level. These two phase clock signals &phgr;
1
and &phgr;
2
can be produced from a single phase clock signal by using it as it is and by inverting it. The clock signal &phgr;
1
is applied to clock input terminals of the domino logic circuit
510
and the latch circuit
540
, and the clock signal &phgr;
2
is applied to clock input terminals of the domino logic circuit
520
and the latch circuits
530
and
550
.
The domino logic circuit
510
is precharged when the clock signal &phgr;
1
is in L level. The domino logic circuit
510
starts evaluation by using logical values of signals inputted from the latch circuit
530
when the clock signal &phgr;
1
becomes H level, and supplies an output signal to the latch circuit
540
. When the clock signal &phgr;
1
is in H level, the clock signal &phgr;
2
is in L level, so that the domino logic circuit
520
is precharged. The latch circuit
540
passes the output signal of the domino logic circuit
510
to the domino logic circuit
520
as it is during a period the clock signal &phgr;
1
is in H level. Also, the latch circuit
540
stores the output signal of the domino logic circuit
510
at a timing the clock signal &phgr;
1
changes from H level to L level.
After the clock signal &phgr;
1
again becomes L level and during a period the domino logic circuit
510
is precharged, the latch circuit
530
outputs the stored output of the domino logic circuit
510
to the domino logic circuit
520
. When the clock signal &phgr;
1
is in L level, the clock signal &phgr;
2
is in H level, so that the domino logic circuit
520
starts evaluation by using logical values of signals inputted from the latch circuit
540
and supplies an output signal to the latch circuit
550
. The latch circuit
550
stores the output signal of the domino logic circuit
520
at a timing the clock signal &phgr;
2
changes from H level to L level.
As mentioned above, during a period the domino logic circuit
510
is performing evaluation, the dom

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