Domino logic circuits, systems, and methods with precharge contr

Details Domino logic circuits, systems, and methods with precharge contr Domino logic circuits, systems, and methods with precharge contr

1998-05-08

2000-03-21

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

329 93, 329 94, 329 95, 329 96, 329 97, 329 98, 329 17, 329112, 329119, 329121, H03K 19096, H03K 19094, H03K 1901

Patent

active

060407166

ABSTRACT:
A logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20.sub.PN, 22.sub.PN), a coupling device (20.sub.PT, 22.sub.PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, and a discharge path (20.sub.L and 20.sub.DT, 22.sub.L and 22.sub.DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase. Further, each of the domino logic circuits comprises an inverter (20.sub.IN, 22.sub.IN) coupled to the precharge node and providing an output responsive to a voltage at the precharge node. The output of the inverter of the first phase domino logic circuit is connected to control the conduction of the discharge path of the second phase domino logic circuit. The logic circuit further comprises a conductor for providing a clock signal (CLOCK), and circuitry for commencing the evaluate phase of the first phase domino logic circuit at a first time (t1) in response to the clock signal transitioning from a first state to a second state. Still further, the logic circuit comprises circuitry for commencing the evaluate phase of the second phase domino logic circuit at a second time (t2) following the first time, and circuitry (26, 28) for commencing the precharge phase of the first phase domino logic circuit at a third time (t2.sub.b) following the second time. The third time corresponds to the latest of a plurality of events. A first of the plurality of events is the clock signal transitioning from the second state to the first state. A second of the plurality of events is the discharge path of the second phase domino logic circuit having sufficient time following a beginning of the evaluate phase of the second domino logic circuit to conduct to cause the voltage at the precharge node of the second phase domino logic circuit to transition to a level sufficient to trigger the output of the inverter of the second phase domino logic circuit.

REFERENCES:
patent: 5453708 (1995-09-01), Gupta

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