Domino logic circuit techniques for suppressing subthreshold...

Details Domino logic circuit techniques for suppressing subthreshold... Domino logic circuit techniques for suppressing subthreshold...

2007-01-31

2010-12-21

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

07855578

ABSTRACT:
Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power as compared to the standard dual threshold voltage domino logic circuits at both the high and low die temperatures. The energy overheads of the circuit techniques may be low, justifying the activation of the proposed sleep schemes by providing net savings in total power consumption during short idle periods.

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