Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-04-06
2001-11-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000
Reexamination Certificate
active
06316960
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to logic circuitry and in particular the present invention relates to logic circuitry having dynamic pull-down circuitry.
BACKGROUND OF THE INVENTION
In the field of semiconductor devices, the frequency of operation of the devices is constantly increasing. For clocked logic devices, therefore, signal evaluation time is decreasing. That is, the time allotted for a logic input to propagate to a logic output is decreasing. Domino circuits are used in integrated circuits to speed operating time. In a domino circuit, data is received on a first transition of a clock, and the signal is coupled to other circuitry on a next transition of the clock.
Conventional domino circuitry includes dynamic circuitry coupled to static gate circuits. The dynamic circuitry pre-charges an input of the static circuitry when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry includes n-type metal oxide semiconductor (NMOS) pull-down circuitry. If the NMOS pull-down circuitry comprises low threshold voltage transistors, the domino circuitry is susceptible to noise.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a domino circuit which has adequate noise margin even when low threshold voltage transistors are used.
SUMMARY OF THE INVENTION
In one embodiment, a domino logic circuit is coupled to receive a clock signal and an input data signal. The domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal, and having a threshold voltage which is less than 0.3 volts.
In another embodiment, a circuit comprises an n-channel pull-down transistor coupled between an output node and a low voltage connection. A gate connection of the n-channel pull-down transistor is coupled to receive a clock signal. A first inverter circuit has an input connection coupled to the output node and an output connection coupled to an input connection of a second inverter circuit. The second inverter circuit has an output connection coupled to the output node. A pull-up n-channel transistor is provided which has a drain connected to an upper voltage node and a source coupled to the output node. A gate connection of the pull-up n-channel transistor is coupled to receive an input data signal. The pull-up n-channel transistor has a threshold voltage which is less than 0.3 volts.
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Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tokar Michael
Tran Anh
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