Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-12-29
2001-08-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S095000
Reexamination Certificate
active
06275071
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to logic circuitry and in particular the present invention relates to improved domino-type logic circuitry.
BACKGROUND OF THE INVENTION
In the field of semiconductor devices, the frequency of operation of the devices is constantly increasing. For clocked logic devices, therefore, signal evaluation time is decreasing. That is, the time allotted for a logic input to propagate to a logic output is decreasing. Domino circuits are used in integrated circuits to speed operating time. In a domino circuit, data is received on a first transition of a clock, and the signal is coupled to other circuitry on a next transition of the clock.
Conventional domino circuitry includes dynamic circuitry coupled to static gate circuits. The dynamic circuitry pre-charges an input of the static circuitry when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry includes n-type metal oxide semiconductor (NMOS) pull-down circuitry. If the NMOS pull-down circuitry comprises low threshold voltage transistors, the domino circuitry is susceptible to noise.
The pull-down circuitry can comprise serially coupled pull down transistors. The speed of this serial pull-down circuitry can adversely impact the operation of the domino circuit by slowing the operation, or increasing noise susceptibility.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a domino circuit which has good operation speed characteristics. There is also a need for a domino circuit that has adequate noise immunity.
SUMMARY OF THE INVENTION
In one embodiment, a domino circuit comprises a dynamic circuit stage having at least one data input node to receive an input data signal, and a clock input node to receive a clock signal. The dynamic circuit provides an output data signal on an output data node when the clock signal is a first state. The domino circuit further comprises a static circuit stage having an input node coupled to receive the output data signal from the dynamic circuit stage. The static circuit stage comprises a plurality of series coupled pull-up transistors coupled to the input, and a precondition circuit coupled to a first intermediate node located between the plurality of pull-up transistors. The precondition circuit provides either a pre-charge or discharge voltage to the first intermediate node when the clock signal is in a second state.
In another embodiment, a domino circuit comprises a dynamic stage circuit having an output connection. The dynamic stage circuit comprises a first pull-up transistor coupled to the output connection, a latch circuit coupled to the output connection, and a plurality of pull-down transistors coupled to the output connection. The dynamic stage circuit further comprises a pre-charge transistor coupled to a first intermediate node of the plurality of pull-down transistors. The domino circuit also comprises a static stage circuit having an input node coupled to the output connection of the dynamic stage circuit. The static stage circuit comprises an output node and a plurality of pull-up transistors connected in series between the output node and an upper voltage supply connection. A discharge transistor is coupled to a second intermediate node of the plurality of pull-up transistors.
In yet another embodiment, a domino circuit comprises a dynamic stage circuit having an output connection. The static stage circuit comprises a first pull-up transistor coupled to the output connection, a latch circuit coupled to the output connection, and a plurality of pull-down transistors coupled to the output connection. The dynamic stage circuit further comprises a discharge transistor coupled to a first intermediate node of the plurality of pull-down transistors. The domino circuit further comprises a static stage circuit having an input node coupled to the output connection of the dynamic stage circuit. The static stage circuit comprises an output node and a plurality of pull-up transistors connected in series between the output node and an upper voltage supply connection. A pre-charge transistor is coupled to a second intermediate node of the plurality of pull-up transistors.
REFERENCES:
patent: 4571510 (1986-02-01), Seki et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5115150 (1992-05-01), Ludwig
patent: 5258666 (1993-11-01), Furuki
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5543735 (1996-08-01), Lo
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5661675 (1997-08-01), Chin et al.
patent: 5671151 (1997-09-01), Williams
patent: 5748012 (1998-05-01), Beakes et al.
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5815005 (1998-09-01), Bosshart
patent: 5825208 (1998-10-01), Levy et al.
patent: 5831990 (1998-11-01), Queen et al.
patent: 5852373 (1998-12-01), Chu et al.
patent: 5889417 (1999-03-01), Klass et al.
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 5896399 (1999-04-01), Lattimore et al.
patent: 5898330 (1999-04-01), Klass
patent: 5917355 (1999-06-01), Klass
patent: 5942917 (1999-08-01), Chappell et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6049231 (2000-04-01), Bosshart
patent: 6052008 (2000-04-01), Chu et al.
patent: 6060910 (2000-05-01), Inui
patent: 6087855 (2000-07-01), Frederick, Jr. et al.
patent: 6108805 (2000-08-01), Rajsuman
patent: 6133759 (2000-10-01), Beck et al.
patent: 4-239221 (1992-08-01), None
patent: 0954101 (1999-03-01), None
Bryant, R.E., “Graph-Based Algorithms for Boolean Function Manipulation”,IEEE Transactions on Computers, C-35(8) , pp. 677-691, (1986).
Chakradhar, S.T., et al., “An Exact Algorithm for Selecting Partial Scan Flip-Flops”, Proceedings of the 31st Design Automation Conference, San Diego, California, pp. 81-86, (1994).
Chakravarty, S., “On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits”, 27th Annual Allerton Conference on Communication, Control, and Computing, Allerton House, Monticello, Illinois, pp. 730-739, (1989).
Patra, P., et al., “Automated Phase Assignment for the Synthesis of Low Power Domino Circuits”, Proceedings of the 36th ACM/IEEE Conference on Design Automation, pp. 379-384, (1999).
Puri, et al., “Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis”, International Conference on Computer Aided Design, 7 p., (1996).
De Vivek K.
Narendra Siva G.
Ye Yibin
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tan Vibol
Tokar Michael
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