Domino comparator capable for use in a memory array

Details Domino comparator capable for use in a memory array Domino comparator capable for use in a memory array

2005-08-09

2005-08-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S049130, C365S189080

Reexamination Certificate

active

06928005

ABSTRACT:
A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.

REFERENCES:
patent: 4740971 (1988-04-01), Tam et al.
patent: 5754463 (1998-05-01), Henstrom et al.
patent: 5862085 (1999-01-01), De Lange
patent: 6859376 (2005-02-01), Kanazawa et al.

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