DMOS transistor with low on-resistance and method of fabrication

Details DMOS transistor with low on-resistance and method of fabrication DMOS transistor with low on-resistance and method of fabrication

1996-12-31

1998-02-17

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257342, H01L 2978

Patent

active

057194211

ABSTRACT:
A DMOS transistor (50) includes an Nwell (70); a Dwell (76) formed in the Nwell (70); a source region (78) formed in the Dwell (78), a channel region (80) defined between an edge of the source region (78) and an edge of the Nwell (70); a gate (86) extending over the channel region (80); and a p+ backgate contact region (90) formed in the source region (78) so as to counterdope and extend through a first portion of the source region (78) to contact the Dwell (76). The formation of the p+ backgate contact region through the source region (78) eliminates the need for a large annular shaped source region resulting in a considerable reduction in both device area and on-resistance.

REFERENCES:
patent: 4843441 (1989-06-01), Willard
patent: 4914051 (1990-04-01), Huie et al.
patent: 4952991 (1990-08-01), Kayama
patent: 5086332 (1992-02-01), Nakagawa et al.
patent: 5171699 (1992-12-01), Hutter et al.
patent: 5250449 (1993-10-01), Kuroyamagi
patent: 5317180 (1994-05-01), Hutter et al.

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