Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-29
2003-04-15
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S334000, C257S335000, C257S337000, C438S212000, C438S330000
Reexamination Certificate
active
06548860
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to current switching DMOS transistors having a gate formed in a trench and in particular to a trench DMOS transistor having a lower resistance when the device is turned on.
BACKGROUND OF THE INVENTION
Power DMOS transistors are widely used in numerous applications, including automotive electronics, disk drives and power supplies. Generally, these devices function as switches, and they are used to connect a power supply to a load. It is important that the resistance of the device be as low as possible when the switch is closed. Otherwise, power is wasted and excessive heat may be generated.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
Such a device is illustrated in
FIG. 1
, which is a cross-sectional view of a single cell of a DMOS transistor
100
, and in
FIG. 2
, which is a perspective cross-sectional view of the cell. Gates
102
and
104
are formed in trenches and surrounded by gate oxide layers
106
and
108
, respectively. The trenched gate is often formed in a grid pattern, the grid representing a single interconnected gate, but a trench gate may also be formed as a series of distinct parallel stripes.
DMOS transistor
100
is a double-diffused device that is formed in an N-epitaxial layer
111
. An N+ source region
112
is formed at the surface of epitaxial layer
111
, as is a P+ contact region
114
. A P-body
116
is located below N+ source region
112
and P+ contact region
114
. A metal source contact
118
makes contact with the N+ source region
112
and shorts the N+ source region
112
to the P+ contact region
114
and P region
116
.
The N-epitaxial layer
111
is formed on an N+ substrate
120
, and a drain contact (not shown) is located at the bottom of the N+ substrate
120
. The contacts
121
for the gates
102
and
104
are shown in
FIG. 2
, which are made by extending the conductive gate material outside of the trench and forming a metal contact at a location remote from the individual cells.
FIG. 3
also shows the gate metal contacts
121
forming the connection to gates
102
and
104
. The gate is typically made of polysilicon doped with phosphorus or boron. It should be noted that when a series of transistor cells are formed, gate contacts
121
only extend from those cells on the periphery of the structure and not from interior cells.
A region
110
of N-epitaxial layer
111
between the N+ substrate
120
and the P+ body
116
is generally more lightly doped with N-type impurities than is N+ substrate
120
. This increases the ability of DMOS transistor
100
to withstand high voltages. Region
110
is sometimes referred to as a “lightly doped” or “drift” region (“drift” referring to the movement of carriers in an electric field). Drift region
110
and N+ substrate
120
constitute the drain of DMOS transistor
100
.
DMOS transistor
100
is an N-channel transistor. When a positive voltage is applied to gate
102
, a channel region within P-body
116
adjacent the gate oxide
106
becomes inverted and, provided there is a voltage difference between the N+ source region
112
and the N+ substrate
120
, an electron current will flow from the source region through the channel region into the drift region
110
. In drift region
110
, some of the electron current spreads diagonally at an angle until it hits the N+ substrate
120
, and then it flows vertically to the drain. Other portions of the current flow straight down through the drift region
110
, and some of the current flows underneath the gate
102
and then downward through the drift region
110
.
The gates
102
and
104
are doped with;a conductive material. Since DMOS transistor
100
is an N-channel device, gates
102
and
104
could be polysilicon doped with phosphorus. Gates
102
and
104
are insulated from the remainder of DMOS transistor
100
by the gate oxide layers
106
and
108
, respectively. The thickness of gate oxide layers
106
and
108
is chosen to set the threshold voltage of DMOS transistor
100
and may also influence the breakdown voltage of DMOS transistor
100
.
In DMOS transistor
100
shown in
FIGS. 1-3
, P+ contact region
114
extends downward below the bottom of the trench to form a deep-heavily doped P body
116
at the center of the cell. In other known DMOS transistors (not shown), the P+ contact region
114
is quite shallow and does not extend below the level of the trench. That is, P+ body
116
is eliminated in these devices. A shallow p+ contact region helps ensure that P-type dopant does not get into the channel region, where it would tend to increase the threshold voltage of the device and cause the turn-on characteristics of the device to vary from one run to another depending on the alignment of the P+ contact region
114
. However, with a shallow P+ contact region
114
that eliminates P+ body
116
, the device can withstand only relatively low voltages (e.g. 10 volts) when it is turned off. This is because the depletion spreading around the junction between P+ contact region
114
and drift region
110
does not adequately protect the corners of the trench (e.g., corner
122
shown in FIG.
1
). As a result, avalanche breakdown may occur in the vicinity of the trench, leading to a high generation rate of carriers which can charge or degrade the gate oxide
106
or even, in an extreme case, cause a rupture in the gate oxide
106
. Thus such a known DMOS transistor is at best a low voltage device.
As previously mentioned, however, in the known DMOS transistor
100
shown in
FIGS. 1-3
, the breakdown voltage is increased by extending the P+ contact region
114
downward below the bottom of the trench to form a deep, heavily-doped P body region
116
at the center of the cell. While this provides additional shielding at corner
122
, the primary advantage is that carrier generation occurs primarily at the bottom tip
302
of the P+ body
116
. This occurs because the electric field is strengthened beneath the tip
302
, thereby causing carriers to be generated at that point or along the curvature of the junction rather than adjacent the gate oxide
106
. This reduces the stress on gate oxide
106
and improves the reliability of DMOS transistor
100
under high voltage conditions, even though it may reduce the actual junction breakdown of the device. Additional details concerning the downwardly extending P contact regions may be found, for example, in U.S. Pat. Nos. 5,072,266 and 5,688,725.
The deep P+ body
116
in DMOS transistor
100
, while greatly reducing the adverse consequences of breakdown, also has some unfavorable effects. First, an upward limit on cell density is created, because with increasing cell density P ions may be introduced into the channel region. As described above, this tends to increase the threshold voltage of the DMOS transistor. Second, the presence of a deep P+ contact body
116
tends to pinch the electron current as it leaves the channel and enters the drift region
110
. In those known transistors that do not include a deep P+ body
116
, the electron current spreads out when it reaches the drift region
110
. This current spreading increases the average current per unit area in the drift region
110
and therefore reduces the on-resistance of the DMOS transistor. The presence of a deep P+ body
116
limits this current spreading and increases the on-resistance co
Hshieh Fwu-Iuan
So Koon Chong
Tsui Yan Man
General Semiconductor Inc.
Kang Donghee
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
Thomas Tom
LandOfFree
DMOS transistor structure having improved performance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DMOS transistor structure having improved performance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DMOS transistor structure having improved performance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073987