DMOS power transistor with reduced number of contacts using inte

Details DMOS power transistor with reduced number of contacts using inte DMOS power transistor with reduced number of contacts using inte

1996-12-31

1999-02-02

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257332, H01L 2976, H01L 2994, H01L 31062

Patent

active

058669310

ABSTRACT:
Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

REFERENCES:
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5168331 (1992-12-01), Yilmaz
patent: 5341011 (1994-08-01), Hshieh et al.
Constantin Bulucea and Rebecca Rossen, "Trench DMOS Transistor Technology for High-Current (100 A Range) Switching," Solid-State Electronics, vol. 34, No. 5, pp. 493-507, 1991.

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