DMA with dynamically assigned channels, flexible block boundary

Details DMA with dynamically assigned channels, flexible block boundary DMA with dynamically assigned channels, flexible block boundary

1997-04-30

2000-11-28

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 22, 710 26, 710 28, 710 10, 710 19, G06F 1328, G06F 1342, G06F 13364

Patent

active

06154793&

ABSTRACT:
An improved DMA controller is provided. The improved DMA controller uses a peripheral control bus which has scan codes to indicate the DMA channel, conventional data request/data acknowledge lines, and additional lines indicating a "terminate," "type fetch," "end of buffer" and "store status." List entries are associated with the buffers in the memory. Each list entry has a type/status field which can be coded with information indicating "ready buffer," whether to notify "end of buffer," "buffer in progress," "completed buffer without status," "completed buffer with status," "ready buffer with command," and "ready buffer without command." The type of status byte can be checked before processing the buffers.

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