Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-07-24
2001-03-27
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S060000, C714S708000
Reexamination Certificate
active
06209046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer unit, a disk unit, and a data transfer method which are employed in hard disk drives (HDDs), and more particularly to a data transfer unit, a disk unit, and a data transfer method equipped with a data transfer function.
2. Description of Related Art
Ultra ATA is an interface standard for enhanced integrated device electronics (EIDE) that has been standardized as the next version of the Fast ATA-3 version to realize fast transfer rate.
The Ultra ATA supports an ultra direct memory access (DMA)/33 transfer protocol and the maximum data transfer rate is 33M bytes/sec. The data transfer by a DMA mode makes it possible to transfer data directly between main memory and peripheral equipment, such as HDDS, without having recourse to intervention of a central processing unit (CPU). The present ultra DMA/33 prescribes three modes: transfer mode
0
through mode
2
, depending upon transfer rates.
The data transfer rate of the Ultra DMA transfer mode is double that of the Multi-word DMA transfer mode of the Fast ATA-3, as shown in Table 1.
TABLE 1
Ultra DMA Transfer
Multi-word DMA Transfer
Mode 0
16.6 MB/s (120 ns)
8.3 MB/s (240 ns)
Mode 1
22.2 MB/s (90 ns)
11.1 MB/s (180 ns)
Mode 2
33.3 MB/s (60 ns)
16.6 MB/s (240 ns)
Also, in the Ultra ATA, a data sending side (for example, a hard disk drive during a read operation and a host during a write operation) drives a strobe signal which determines the timing at which data is fetched, thereby controlling data transfer rate at the data sending side. In fact, the data transfer rate at the hard disk drive is set by a Set Features command (EFh) from the host, and the data transfer rate will be reset if the hard disk drive receives a power-on reset or hard reset signal from the host.
Thus, in the Ultra DMA transfer protocol, since the data transfer rate is increased twice, there is a need to detect an error in the data transferred onto the IDE I/F bus, and there is added a cyclic redundancy check (CRC) function which calculates the CRC value of transferred data at the host and the hard disk drive and compares the calculated CRC value.
Where an error is detected by the aforementioned CRC function, the host merely reissues the command to the disk drive. However, in the case where temporarily the signal quality on the IDE I/F bus becomes degraded and a CRC error frequently occurs, the number of command reissue is increased, and consequently, an extreme reduction in the throughput of data transfer takes place. Furthermore, when a CRC error cannot be recovered by command reissue alone, the entire system will be stopped.
Accordingly, it is an object of the present invention to provide a data transfer unit, a disk drive, and a data transfer method which are capable of decreasing the cases in an Ultra DMA transfer mode of extreme reductions in the throughput of data caused by the command reissue and a final system stop. An example would be a temporary CRC error frequently occurring during the data transfer on Read DMA Commands which can be fixed by only a change on the disk drive side without requiring any changes of the existing mechanism on the host side. It is an object of the invention to realize highly reliable data transfer and a minimum reduction in the throughput of data transfer.
Another object of the present invention is to provide similar improvements in an Ultra DMA transfer mode for problems caused by command reissue and a final system stop.
Still another object of the present invention is to provide a solution which is capable of transferring data without errors in an Ultra DMA transfer mode.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a data transfer unit for transferring data in a direct memory access (DMA) transfer mode between a storage unit and a host, wherein a slower data transfer rate is established when a predetermined error is detected. In one embodiment the cyclicity of the error occurrence calculated and a wait is inserted between data to avoid the calculated cyclicity of the detected error. Optionally the data transfer unit may return the data transfer rate to the original data transfer rate, state or a default state after a predetermined time has elapsed, after a predetermined number of commands have been received, after a predetermined amount of data have been transferred, or by combination of these.
The aforementioned DMA transfer mode may also be based upon an Ultra DMA transfer mode.
In accordance with the present invention, there is provided a method of transferring data to and from a storage unit and a host, comprising the steps of: setting a first data transfer rate; transferring data between the storage unit and the host at the first data transfer rate; detecting an error in the transferred data; setting the data transfer rate to a second data transfer rate slower than the first data transfer rate when a predetermined error is detected; and transferring data at the second transfer rate.
REFERENCES:
patent: 4153916 (1979-05-01), Miwa et al.
patent: 5826106 (1998-10-01), Pang
patent: 6035425 (2000-03-01), Caldwell et al.
Asano Hideo
Kakihara Toshio
Kanamaru Atsushi
Oshikawa Hiroshi
Sato Masahiko
International Business Machines - Corporation
Kim Kenneth S.
Knight G. Marlin
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