Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-11-29
2003-10-14
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S005000, C710S040000, C710S052000, C710S111000, C710S308000
Reexamination Certificate
active
06633926
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a direct memory access (DMA) transfer device that is capable of DMA transfer to/from a memory that can be accessed in page units at high speed.
(2) Description of the Related Art
A DMA transfer device transfers data between/within memories or between a memory and an input/output (I/O) device at high speed.
To perform DMA transfer between memories connected to the same bus or between different storage regions in the same memory, the DMA transfer device reads data from one storage region (hereafter called a “read region”), temporarily places the read data in a buffer in the DMA transfer device, and writes the data from the buffer into another storage region (hereafter called a “write region”). This buffer has a capacity equal to or larger than the data that can be transferred through one access to the memory. Hereafter, the size of data to be transferred though one access to a storage region is called the “access data size”. Typical conventional DMA transfer devices read, buffer, and write data in units of the access data size. By doing so, the buffer size can be minimized.
If a DMA transfer device has a buffer capacity of an integral multiple of the access data size, the device will first perform repeated accesses to the read region to read and buffer an amount of data equal to the buffer capacity, before performing repeated accesses to write this data into the write region.
In recent years, Synchronous Dynamic RAM (SDRAM) that can be accessed in page units at high speed is widely used as main memory. Here, a “page” refers to a group of consecutive locations in a memory that holds a predetermined amount of data, and a high-speed access to consecutive addresses within a page is hereafter called a “high-speed page access”. Conventional DMA transfer devices, however, access SDRAM using the access data size or buffer size as described above, not page units, and so cannot make the most of the high-speed performance of SDRAM.
SUMMARY OF THE INVENTION
The first object of the present invention is to provide a DMA transfer device which, by performing high-speed access, makes full use of the page access capability of a memory.
The second object of the present invention is to provide a DMA transfer device that can perform data transfer at high speed by rationally dividing up a region to be accessed.
The third object is to provide a DMA transfer device suited to accessing a memory allowing high-speed page access.
The fourth object is to provide a DMA transfer device that can suspend, when a DMA transfer request of a higher priority is issued during a DMA transfer of a lower priority, the lower-priority DMA transfer to perform the higher-priority DMA transfer, and that can reduce the idle time of buses used by DMA transfer.
In order to achieve the above first to third objects, a DMA transfer device of the present invention accesses a region in a memory allowing high-speed page access, the DMA transfer device including a detecting unit for detecting access areas that form the region to be accessed, each access area being demarcated by a page boundary and one of: (1) a start of the region; (2) an end of the region; and (3) another page boundary, and an access unit for performing high-speed page access to each access area.
With this construction, when at least one of the read and write regions exists in a memory allowing high-speed page access, the DMA transfer device can perform high-speed page access to each access area between page boundaries in the read/write region. Accordingly, the present DMA transfer device can make full use of the page access capability of the memory, reduce the idle time of buses, and reduce the time taken by the entire DMA transfer.
Here, the detecting unit may include: an address updating unit for storing an access address whose initial value is a start address of the region to be accessed and for updating the access address, whenever the access unit has performed an access, to a start address of a remaining part of the region to be accessed; a remaining data size updating unit for storing a remaining data size whose initial value is a data size of the region to be accessed and for updating the remaining data size, whenever the access unit has performed an access, to a data size of the remaining part of the region to be accessed; and an access area detecting unit for detecting an access area as an area from the access address to a next page boundary when the access address is set at the initial value and for otherwise detecting an access area as an area from the access address to either a next page boundary or the end of the region to be accessed.
With this construction, the DMA transfer device can detect an access area that can be one of: an area from the access address at the start of the region to be accessed to the next page boundary; an area from the page boundary to the next page boundary; . . . and an area from a page boundary to the end of the region one by one while at the same time having the access unit perform high-speed page access to a detected access area.
Here, the access area detecting unit may include a size detecting unit for detecting a size of an area from the access address in the address updating unit to either the next page boundary or the end of the region, and a size storing unit for storing the detected area size as a size of the access area. The access unit may perform high-speed page access to the area of the access area size in the size storing unit, starting from the access address in the address updating unit.
For this construction, the access unit can be supplied with suitable parameters for high speed access due to the access area detecting unit detecting access areas as combinations of a start address and a size of the access area.
Here, the size detecting unit may include: a subtracting unit for subtracting a value, which is indicated by lower bits of the access address and shows a relative position of the access address within a page in the memory, from a page size of each page to produce a subtraction result; a comparing unit for comparing the subtraction result with the remaining data size to produce a comparison result; and a selecting unit for selecting, based on the comparison result, one of the subtraction result and the remaining data size to give a smallest selection result, wherein the size storing unit may store the selection result as the access area size.
With this construction, the size detecting unit can detect an access area size using only a simple construction that performs a subtraction and a comparison.
The first to third objects can be also achieved by a DMA transfer device that transfers data from a first region to a second region in memories that allow high-speed page access, the DMA transfer device including: a first detecting unit for detecting a plurality of read areas that form the first region, each read area being demarcated by a page boundary and one of: (1) a start of the first region; (2) an end of the first region; and (3) another page boundary; a second detecting unit for detecting a plurality of write areas that form the second region, each write area being demarcated by a page boundary and one of: (1) a start of the second region; (2) an end of the second region; and (3) another page boundary; a buffer unit for temporarily storing data to be transferred; and an access unit for performing high-speed page access to each of the read areas and each of the write areas.
When both the read (first) and write (second) regions exist in a memory or memories allowing high-speed page access, the DMA transfer device can perform high-speed page access to each read area between page boundaries in the read region and to each write area in the write region. As a result, idle time of buses can be reduced, and therefore the entire DMA transfer can be quickly performed.
Here, the first region and the second region may exist in either in a same memory or different memories connected to a same bus, wherein the access unit may inc
Harada Masaaki
Sekibe Tsutomu
LandOfFree
DMA transfer device capable of high-speed consecutive access... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DMA transfer device capable of high-speed consecutive access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DMA transfer device capable of high-speed consecutive access... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168882