DMA scheduling mechanism

Details DMA scheduling mechanism DMA scheduling mechanism

2005-02-08

2005-02-08

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S006000, C710S062000, C709S209000

Reexamination Certificate

active

06854025

ABSTRACT:
A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

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