Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2002-06-27
2004-11-23
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S004000, C710S033000, C711S100000, C712S225000
Reexamination Certificate
active
06823403
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to DMA (Direct Memory Access) controller devices and methods, and in particular to DMA mechanisms that allow direct memory access over a high-speed packet bus, such as in HyperTransport™ based USB-2 (Universal Serial Bus) host controllers.
2. Description of the Related Art
In present computer systems, one way of relieving the central microprocessing unit of performing repetitive input/output functions is to avoid interrupts and to realize these functions by means of a DMA controller which is a control unit that enables direct memory access. Before the actual input/output process takes place, the processor initializes the DMA controller by writing initialization data to its registers, and the DMA controller is then able to independently perform data transfers between memory and interface. That is, during the phase where the control and address registers are initialized, the controller acts as slave. However, as soon as the controller receives a transfer request and begins data transmission, the controller independently performs bus cycles, i.e. it acts as master and shares the bus with the processor, for memory access.
FIG. 1
depicts a conventional system employing a DMA controller. In this system, the processor
100
is connected to the memory
105
, the DMA controller
110
and a device control unit
120
that controls the peripheral device
125
. Dependent on the mode of operation of the DMA controller
110
, the data transfer between memory
105
and device control unit
120
may be performed directly or indirectly, i.e. by means of a buffer
115
. In the direct transfer mode, the DMA controller
110
requires only one bus cycle per data item by addressing the memory
105
via the address bus and at the same time, addressing the interface data registers via a control line (single address mode). In the indirect transfer mode, the DMA controller
110
first performs a read cycle and stores the read data in the buffer
115
. In a subsequent write cycle, the DMA controller
110
then transfers the buffered data to the respective target unit. Memory and interface are both addressed via the address bus (dual address mode).
While there are many different implementations of a DMA controller possible in a computer system, one example is a DMA controller that forms part of a USB 2.0 compliant host controller. USB was originally developed in 1995 to define an external expansion bus which facilitates the connection of additional peripherals to a computer system. The USB technique is implemented by PC (Personal Computer) host controller hardware and software and by peripheral-friendly master-slave protocols and achieves robust connections and cable assemblies. In USB systems, the role of the system software is to provide a uniformed view of the input/output architecture for all applications software by hiding hardware implementation details. In particular, it manages the dynamic attach and detach of peripherals and communicates with the peripherals to discover their identity. During run time, the host initiates transactions to specify peripherals, and each peripheral accepts its transactions and response accordingly.
While these functions and protocols were already implemented in the USB 1.1 specification, this technique was still improved in order to provide a higher performance interface. In USB 2.0 compliance systems, the speed improvement may be up to a factor of 40. Moreover, USB 2.0 is backwards compatible with USB 1.1.
In USB 2.0 compliant hosts, e.g. personal computers, the high-speed USB 2.0 functionality is performed by an enhanced host controller that operates in compliance with the EHCI (Enhanced Host Controller Interface) specification for USB 2.0. While this specification defines the register-level interface and associated memory-resident data structures, it does not define nor describe the hardware architecture required to build a compliant host controller.
To satisfy the demand for high-speed chip-to-chip communication in computer systems, for instance in connection with EHCI compliant USB host controllers, the HyperTransport technology was developed which provides a high-speed, high-performance point-to-point on-board link for interconnecting integrated circuits on a motherboard. It can be significantly faster than other bus technologies for an equivalent number of pins. The HyperTransport technology is designed to provide significantly more bandwidth than current technologies, to use low-latency responses, to provide low pin count, to be compatible with legacy computer buses, to be extensible to new system architecture buses, to be transparent to operating systems, and to offer little impact on peripheral drivers.
While the HyperTransport interface thus provides a high-speed chip-to-chip interface, data processing performed within the chips itself may often become the bottle neck. In particular the present DMA mechanisms may decrease the overall performance since they prevent the full performance provided by on-board interchip interfaces such as the HyperTransport interface from being brought down to the peripherals.
SUMMARY OF THE INVENTION
A DMA mechanism is provided that may improve the performance in particular when performing direct memory access over a high-speed packet bus.
In one embodiment, a DMA controller device is provided that has a transmit DMA engine for outputting read requests to a memory interface and receiving requested data from the memory interface. The transmit DMA engine comprises a data transfer initiating unit for initiating a data transfer by determining which data is to be fetched from memory and outputting first address data identifying a first memory range. The first memory range contains the determined data to be fetched. The transmit DMA engine further comprises a boundary alignment unit for receiving the first address data, generating second address data therefrom, and outputting the second address data. The second address data identifies at least one second memory range that differs from the first memory range in at least one boundary. Further, the transmit DMA engine comprises a read request building unit for receiving the second address data and generating at least one read request based thereon.
In another embodiment, there may be provided a DMA controller device that has a receive DMA engine for writing data to a memory interface. The receive DMA engine comprises a write command building unit for determining which data is to be written to memory, determining first address data that identifies a first memory range where the first memory range is the memory range to which the determined data is to be written, and building at least one write command to write the determined data. The write command building unit includes a boundary alignment unit for generating second address data based on the first address data. The second address data identifies at least one second memory range that differs from the first memory range in at least one boundary. The write command building unit is arranged for building the at least one write command to write the determined data to the at least one second memory range.
In a further embodiment, a USB host controller is provided for handling the data traffic between at least one USB device and a system memory of a computer system. The USB host controller comprises a transmit and/or receive DMA engine. The transmit DMA engine is arranged for outputting read requests to a memory interface and receiving requested data from the memory interface. The receive DMA engine is arranged for writing data to the memory interface. The transmit and/or receive DMA engine comprise an address data generating unit for generating and outputting first address data that identifies a first memory range. The first memory range contains the determined data to be fetched, or is the memory range to which the determined data is to be written. The transmit and/or receive DMA engine further comprises a boundary alignment unit for receiving the first a
Gulick Dale E.
Hesse Siegfried Kay
Advanced Micro Devices , Inc.
Chen Alan
Gaffin Jeffrey
Kivlin B. Noäl
Meyertons Hood Kivlin Kower & Goetzel, P.C.
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