Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-10-01
2004-03-02
Vo, Tim (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S022000, C710S026000, C710S306000
Reexamination Certificate
active
06701405
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to microprocessor systems and, more particularly, to a system, method, and mechanism providing direct memory access (DMA) between system components and memory without imposing on the processor.
2. Relevant Background
Conventional computer architectures facilitate data movement between input/output (I/O) devices and system memory by providing a hardware mechanism that implements Direct Memory Access (DMA). DMA transfer allows data to be read from an I/O device and written to a designated location in memory, or read from a designated location in memory and written to an I/O device without involvement by a central processing unit (CPU). This functionality takes advantage of the fact that hardware controlled system data transfers are often faster than transfers involving the CPU. Also, the CPU is free to perform other useful work while the DMA transfer takes place. Direct memory access (DMA) is a way for computer peripheral devices to communicate with working memory without involving the CPU. DMA is a very fast way of transferring blocks of data when no processing is required and is a conventional method by which hard disks, soundboards and data acquisition equipment send and receive data to and from memory.
A DMA transfer can be initiated by a peripheral or the central processing unit (CPU) itself. A DMA controller coupled to system bus actually manages DMA transfers. The system bus is coupled directly or indirectly to the CPU, peripherals, and the main memory. Most DMA systems provide multiple DMA “channels,” wherein each DMA channel is assigned to a particular I/O device.
Current DMA implementations involve a DMA controller that is closely coupled to the peripherals and system bus. By closely coupled it is meant that a relatively complex interface exists between peripherals using DMA and the DMA controller. This interface enables the peripheral and DMA controller to exchange state information to make the DMA exchange take place and cause the DMAC to issue a DMA transfer acknowledge. Usually this interface must be implemented with a large number of signal wires to handle tasks of initiating, synchronizing, and performing DMA transfers.
These types of implementations are difficult to scale to large numbers of peripherals. The number of signal lines required to implement the complex interface increases with the number of peripherals. The length and complexity of signal lines-becomes restrictive to large system-on-a-chip designs. Moreover, the complex interface imposes a significant overhead in terms of signaling hardware on the peripherals that use DMA. A need exists for a processor implementing DMA and a DMA implementation method with reduced hardware overhead that is readily scaleable and readily implemented in DMA peripherals.
Another limitation of many DMA implementations is that the close coupling of the DMAC with the peripherals makes it difficult to reuse the circuit designs in other implementations. Design reuse is an increasingly important criteria, especially in embedded system design. A need exists for a mechanism and method for coupling DMA components to implement DMA transfers using a general purpose system bus for communication between the components.
SUMMARY OF THE INVENTION
The present invention involves a computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface.
To conduct the DMA transfer the DMAC initiates a LOAD transaction request with a source peripheral specified in DMAC registers. The LOAD transaction is associated with a DMA acknowledge. The peripheral request interface responds to the LOAD transaction request and the DMA acknowledge by initiating peripheral-specific signaling to access data specified by the LOAD request. The peripheral request interface completes the LOAD transaction by supplying a LOAD response to the DMAC over the system bus. The DMAC receives and buffers the LOAD response and initiates a STORE transaction request to transfer the specified data to a destination system component specified by the DMAC registers.
REFERENCES:
patent: 4814981 (1989-03-01), Rubinfeld
patent: 5251311 (1993-10-01), Kasai
patent: 5386565 (1995-01-01), Tanaka et al.
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5440705 (1995-08-01), Wang et al.
patent: 5448576 (1995-09-01), Russell
patent: 5452432 (1995-09-01), Macachor
patent: 5455936 (1995-10-01), Maemura
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5483518 (1996-01-01), Whetsel
patent: 5485624 (1996-01-01), Steinmetz et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5530965 (1996-06-01), Kawasaki et al.
patent: 5570375 (1996-10-01), Tsai et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5596734 (1997-01-01), Ferra
patent: 5598551 (1997-01-01), Barajas et al.
patent: 5608881 (1997-03-01), Masumura et al.
patent: 5613153 (1997-03-01), Arimilli et al.
patent: 5613162 (1997-03-01), Kabenjian
patent: 5627842 (1997-05-01), Brown et al.
patent: 5657273 (1997-08-01), Ayukawa et al.
patent: 5659798 (1997-08-01), Blumrich et al.
patent: 5682545 (1997-10-01), Kawasaki et al.
patent: 5704034 (1997-12-01), Circello
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5724549 (1998-03-01), Selgas et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5751621 (1998-05-01), Arakawa
patent: 5768152 (1998-06-01), Battaline et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5774701 (1998-06-01), Matsui et al.
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5781558 (1998-07-01), Inglis et al.
patent: 5796978 (1998-08-01), Yoshioka et al.
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5832248 (1998-11-01), Kishi et al.
patent: 5835963 (1998-11-01), Yoshioka et al.
patent: 5838993 (1998-11-01), Riley et al.
patent: 5848247 (1998-12-01), Matsui et al.
patent: 5860127 (1999-01-01), Shimazaki et al.
patent: 5862387 (1999-01-01), Songer et al.
patent: 5867726 (1999-02-01), Ohsuga et al.
patent: 5884092 (1999-03-01), Kiuchi et al.
patent: 5896550 (1999-04-01), Wehunt et al.
patent: 5918045 (1999-06-01), Nishii et al.
patent: 5930523 (1999-07-01), Kawasaki et al.
patent: 5930833 (1999-07-01), Yoshioka et al.
patent: 5933654 (1999-08-01), Galdun et al.
patent: 5944841 (1999-08-01), Christie
patent: 5950012 (1999-09-01), Shiell et al.
patent: 5953538 (1999-09-01), Duncan et al.
patent: 5956477 (1999-09-01), Ranson et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 5978902 (1999-11-01), Mann
patent: 5983017 (1999-11-01), Kerr et al.
patent: 5983379 (1999-11-01), Warren
patent: 6000043 (1999-12-01), Abramson
patent: 6111592 (2000-08-01), Yagi
patent: 6185634 (2001-02-01), Wilcox
patent: 6219725 (2001-04-01), Diehl et al.
patent: 6415338 (2002-07-01), Habot
patent: 0165600 (1991-11-01), None
patent: 0636976 (1995-02-01), None
patent: 0652516 (1995-05-01), None
patent: 0702239 (1996-03-01), None
patent: 0720092 (1996-07-01), None
patent: 0933926 (1999-08-01), None
pate
Adusumilli Vijaya Pratap
Hasegawa Atsushi
Naruse Takanobu
Ramanadin Bernard
Yoshioka Shin-ichi
Hitachi , Ltd.
Townsend and Townsend / and Crew LLP
Vo Tim
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