DMA controller with split channel transfer capability and FIFO b

Details DMA controller with split channel transfer capability and FIFO b DMA controller with split channel transfer capability and FIFO b

1998-04-03

2000-11-07

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 3, 710 19, 710 20, 710 21, 710 23, 710 24, 710 25, 710 30, 710 33, 710 34, 710 48, 710 52, G06F 300, G06F 1328, G06F 1300, G06F 1314

Patent

active

061450278

ABSTRACT:
A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.

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