DMA controller with semaphore communication protocol

Details DMA controller with semaphore communication protocol DMA controller with semaphore communication protocol

1997-03-27

2000-04-25

Palys, Joseph E.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

G06F 1200

Patent

active

060555831

ABSTRACT:
A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.

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