DMA controller with dynamically variable access priority

Details DMA controller with dynamically variable access priority DMA controller with dynamically variable access priority

2000-03-07

2003-09-02

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S033000, C710S052000, C711S105000

Reexamination Certificate

active

06615291

ABSTRACT:

This application is based on applications Nos. 11-060441, 11-064388, 11-066451, 11-073181, 11-081218, 11-085210 and 11-357320 filed in Japan, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to direct memory access control (referred to as DMA control hereinafter). More particularly, the present invention relates to a direct memory access controller which can appropriately reconcile pluralities of memory access made by a plurality of devices connected to a common bus in accordance with operation state of the devices. For example, such a DMA controller is applicable to a copier wherein CPU and other devices such as scanner and printer share a bus.
2. Description of the Prior Art
There has conventionally been known a DMA controller including a bus-use reconcilement section for reconciling pluralities of bus-access based on bus-access requests generated from a plurality of devices.
FIG. 48
shows an example of a conventional DMA control system. Basically, the system shown in
FIG. 48
includes a memory
107
, DMA control sections
101
,
102
,
103
, and an access control section
104
. In the conventional system, the DMA control sections
101
to
103
and the access control section
104
get access to the memory
107
via a common bus
105
. Furthermore, the system has a bus-use reconcilement section
106
for reconciling pluralities of bus-access between the bus
105
and each of the DMA control sections
101
to
103
and the access control section
104
. Still further, DMA control sections
101
,
102
, and
103
are connected to a printer
111
, a scanner
112
, a hard disk
113
, respectively. The access control section
104
is connected to a CPU
114
.
The conventional DMA control system works as follows. See FIG.
49
. For instance, when the DMA control section
101
needs access to the bus
105
, the DMA control section
101
sends a request signal req
1
to the bus-use reconcilement section
106
. If the request is acceptable, the bus-use reconcilement section
106
returns a bus-use permission signal ack
1
in response to the req
1
. While the ack
1
is in an active state, the printer
111
can get access to the bus
105
through the DMA control section
101
. It is same for other devices connected to other DMA control sections.
When those control sections send requests concurrently, the bus-use reconcilement section
106
is designed to return bus-use permission signals to each of the requests in order based on a predetermined priority ranking.
FIG. 50
shows an example of priority ranking for bus-access. In case of
FIG. 50
, when request signals req
1
, req
2
, req
3
, and req
4
are generated concurrently, the bus-use reconcilement section
106
returns a bus-use permission signal ack
1
only since the DMA control section
101
is assigned to the highest in the predetermined priority ranking. Thereby, the DMA control section
101
gets access to the bus
105
prior to the other control sections
102
to
104
. Similarly, when request signals req
2
, req
3
, and req
4
are generated concurrently, the bus-use reconcilement section
106
returns a bus-use permission signal ack
2
only since the DMA control section
102
is assigned to the highest among control sections
102
to
104
. Therefore, the DMA control section
102
gets access to the bus
105
prior to the control sections
103
and
104
.
However, since the conventional DMA controller
100
controls bus-use reconcilement in accordance with the access priority ranking shown in
FIG. 50
, there has been a fear that a device assigned to higher priority such as printer
101
is likely to occupy the system. Furthermore, in a case that request signals req
1
, req
2
, req
3
, and req
4
generated at the DMA control sections
101
,
102
,
103
, and the access control section
104
, respectively, go out to the bus-use reconcilement section
106
intensively, there has been a fear that a device assigned to lower priority, such as the CPU
114
, can hardly get access to the bus
105
. Under such a situation, program for the system is likely to stop because the CPU
114
cannot get access to the bus
105
. What is more, it has been a problem that the conventional DMA controller
100
cannot lower power consumption effectively.
SUMMARY OF THE INVENTION
The present invention is intended to solve the above-described problems of the conventional DMA controller. Its prime object is to provide a DMA controller wherein use-state of a common bus is detected with respect to a plurality of devices so that each of the devices can appropriately get access to a common bus under bus-use reconcilement control based on the detection result. Another object is to provide a DMA controller capable of lowering power consumption appropriately in response to use-sate of a common bus.
In order to achieve the above objectives, the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and bus-use reconcilement means for reconciling pluralities of bus-access made by the devices based on a detection result obtained by the bus monitor means.
The bus monitor means for the DMA controller detects use-state of the common bus with respect to each of the devices every predetermined period. Then, the bus-use reconcilement means reconciles pluralities of bus-access among each of the devices based on the detection result obtained by the bus monitor means. Thereby, pluralities of bus-access among each of the devices are appropriately reconciled in proportion to bus use rate for each of the devices. As a result, bus-occupation by a device assigned to higher priority is avoided even when devices generate requests intensively. Thereby, a device assigned to lower priority can obtain necessary access time. That is, this system enables all the devices connected to the common bus to get access to the bus appropriately. Particularly, this can surely prevent program from stopping.
For detecting use-state of the common bus, the bus monitor means may integrate generation time of bus-use permission signals output from the bus-use reconcilement means. Alternatively, the use-state of the common bus may be detected based on an in-use-state signal the common bus generates. Further, the inventive DMA controller may reject a request from at least one of the devices so as to achieve access reconcilement in accordance with the detection result obtained by the bus monitor means. Preferably, such a request rejection is given to a device assigned to higher priority ranking than a device the ranking of which should be made higher and does not need real time processing.
Thus, the inventive DMA controller changes manners of bus-use reconcilement along with use-state of the common bus with respect to each of the devices connected the bus. Thereby, problems such as that particular device occupies the common bus or, vice versa, particular device can hardly get access to the bus can be avoided.
Furthermore, the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and priority determining means for determining bus-use priority ranking for each of the devices in accordance with a detection result obtained by the bus monitor means. For this type of DMA controller, the bus-use reconcilement means may reconcile pluralities of bus-access made by each of the devices in accordance with the bus-use priority determined by the priority determining means.
In the inventive DMA controller, when the bus monitor means detects use-state of the common bus with respect to each of the devices every pred

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