Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-11-21
2003-11-18
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S052000
Reexamination Certificate
active
06651114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DMA controller and a control method therefor, and more particularly to a DMA controller arranged to transfer data between a main storage and an input-output (I/O) device and a control method for the DMA controller.
2. Description of Related Art
Direct memory access (DMA) is used in a computer system to transfer data between an I/O device and a main storage of the computer system. The DMA is also used for transferring the content of a certain range of the main storage to another range thereof.
The DMA is carried out by a DMA controller which operates independently of a CPU in a computer system. More specifically, the DMA controller has two functions. In one function, the DMA controller causes the I/O device to output data and writes the data into the main storage. In the other function, the DMA controller reads out data from the main storage and causes the I/O device to receive the data. Since other functions or tasks can be carried out by the CPU even while the DMA controller is in operation, the performance of the computer system including such a DMA controller can be greatly enhanced as a whole.
FIG. 2
shows, by way of example, the arrangement of a computer system using a DMA controller. Referring to
FIG. 2
, a CPU
110
is arranged to control the whole computer system. A system bus
100
is connected to the CPU
110
through a bus interface. A RAM
120
is arranged to serve as a main storage. A ROM
130
is arranged to store therein program-executing codes, etc. I/O devices
140
,
150
and
160
are connected to the system bus
100
through system bus interfaces
141
,
151
and
161
, respectively, and are also connected to a DMA controller
180
through a control line
170
. The DMA controller
180
is connected to the system bus
100
and is also connected to each of the I/O devices
140
,
150
and
160
through the control line
170
.
In the case of the example shown in
FIG. 2
, although the DMA controller
180
controls data transfer, data itself does not pass through the DMA controller
180
. While the DMA controller
180
is arranged to issue reading and writing commands for data transfer, data moves directly between the main storage
120
and the I/O device
140
,
150
or
160
through the system bus
100
.
FIG. 3
shows, as another example, the arrangement of a computer system using a DMA controller. Referring to
FIG. 3
, a CPU
210
is connected to a system bus
200
through a bus interface. A RAM
220
is arranged to serve as a main storage. A ROM
230
is arranged to store therein program-executing codes, etc. I/O devices
240
,
250
and
260
are connected to a DMA controller
280
through an I/O bus
270
. The DMA controller
280
is connected to the system bus
200
and is also connected to the I/O devices
240
,
250
and
260
through the I/O bus
270
.
The I/O devices
240
,
250
and
260
and the main storage
220
have different access speeds from each other. Therefore, an FIFO memory
290
is provided inside the DMA controller
280
for buffering the access speed.
In the case of the example shown in
FIG. 3
, while data transfer is controlled by the DMA controller
280
, data itself is read from or written into the main storage (RAM)
220
through the system bus
200
and a bus interface of the DMA controller
280
. Further, the data is transferred between the DMA controller
280
and the I/O devices
240
,
250
and
260
through the I/O bus
270
.
In this instance, in a case where the data width of the I/O device differs from the data width of the main storage, for example, in a case where the data width of the I/O device is 8 bits while the data width of the main storage is 32 bits, a converting action for the data width is performed by using the FIFO memory
290
provided in the DMA controller
280
.
The FIFO memory
290
has a capacity of “width of 32 bits (per word)×an integer” and is arranged to permit masking at arbitrary bit positions in writing data (while keeping original information in the case of masking).
In a case where the direction of data transfer is from the main storage to the I/O device, as shown in
FIG. 4
, data is read out from the main storage word by word, i.e., 32 bits, at a time. The data thus read out is stored at the rearmost word place of the FIFO memory. Data of one foremost word (32 bits) of the FIFO memory is then selected, in four divided blocks, by a selector serially beginning with a byte (8 bits) of higher order one by one. The data read out and selected is thus transferred to one of the I/O devices.
In a case where the direction of data transfer is from the I/O device to the main storage, data is transferred as shown in FIG.
5
. Referring to
FIG. 5
, every time data of one byte (8 bits) is received from the I/O device, the data is stored serially beginning with a byte of higher order within the rearmost word part of the FIFO memory. After that, the whole data of one word (32 bits) is stored by the lump into the main storage from the foremost part of the FIFO memory.
The DMA controller requests the right to gain access to the system bus and, then, acquires the right to gain access to the system bus. In a case where the capacity of the FIFO memory is equal to or more than one word (=4 bytes), data still can be transferred also from the I/O device to the DMA controller concurrently with the request and acquisition of the right to gain access until data is written into the main storage. Therefore, even in a case where a high-speed I/O device is connected, this arrangement permits a reduction in waiting time on the side of the I/O device, so that the possibility of occurrence of overrun of the I/O device can be suppressed. Further, since the frequency of writing into the main storage is reduced to one fourth, the efficiency of use of the system bus can be enhanced.
In a case where, as shown in
FIGS. 4 and 5
, the data width of the system bus is 32 bits while the data width of the I/O bus is 8 bits, data transfer between the DMA controller and each of the I/O devices is carried out in accordance with the following procedures.
In a case where the direction of data transfer is from the main storage to the I/O device, the procedures of data transfer are as follows. 1) One of the I/O devices to which the channel of DMA is to be allotted is first decided. 2) A request signal Req* requesting DMA transfer is asserted by the I/O device to which the DMA channel is allotted. 3) In reply to the request signal Req*, an acknowledgement signal Ack* is immediately sent from the DMA controller to the I/O device if there is data in the FIFO memory. If the FIFO memory is vacant, the DMA controller reads out data of one word from the main storage and stores the data into the FIFO memory. After that, the DMA controller sends an acknowledgement signal Ack* to the I/O device. 4) Concurrently with the acknowledgement signal Ack*, data of one byte is driven onto the I/O bus by the DMA controller. The I/O device takes the data in. 5) The steps 2), 3) and 4) of the procedures are repeated a number of times corresponding to a length of DMA transfer set by the CPU.
In a case where the direction of data transfer is from the I/O device to the main storage, the procedures of data transfer are as follows. 1) One of the I/O devices to which the DMA channel is to be allotted is first decided. 2) A request signal Req* requesting DMA transfer is asserted by the I/O device to which the DMA channel is allotted. Then, data of one byte is driven onto the I/O bus by the I/O device. 3) If the FIFO memory has a vacancy, an acknowledgement signal Ack* is immediately sent from the DMA controller to the I/O device. If the FIFO memory is full and has no vacancy, the DMA controller waits for occurrence of a vacancy in the FIFO memory with writing of data into the main storage finished. After that, the acknowledge signal Ack* is sent to the I/O device. 4) The DMA controller causes data on the I/O bus to be stored into the FIFO memory. If the content of the
Canon Kabushiki Kaisha
Gaffin Jeffrey
Knapp Justin
Robin Blecker & Daley
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