DMA controller utilizing flexible DMA descriptors

Details DMA controller utilizing flexible DMA descriptors DMA controller utilizing flexible DMA descriptors

2007-11-06

2007-11-06

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S029000, C710S033000

Reexamination Certificate

active

10786356

ABSTRACT:
A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

REFERENCES:
patent: 6782465 (2004-08-01), Schmidt
patent: 6799232 (2004-09-01), Wang
patent: 2001/0001867 (2001-05-01), Collier
patent: 2003/0188054 (2003-10-01), Yosimoto et al.
patent: 2004/0208314 (2004-10-01), Patariu et al.
patent: 2005/0076163 (2005-04-01), Malalur

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