DMA controller having programmable channel priority

Details DMA controller having programmable channel priority DMA controller having programmable channel priority

2007-07-03

2007-07-03

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S028000, C710S040000

Reexamination Certificate

active

10786853

ABSTRACT:
A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

REFERENCES:
patent: 4901234 (1990-02-01), Heath et al.
patent: 5655151 (1997-08-01), Bowes et al.
patent: 5826106 (1998-10-01), Pang
patent: 6735639 (2004-05-01), Higuchi
patent: 2004/0215868 (2004-10-01), Solomon et al.

Affiliated with

Also associated with

Rating

DMA controller having programmable channel priority does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DMA controller having programmable channel priority, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DMA controller having programmable channel priority will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3795809