DMA controller for controlling and measuring the bus...

Details DMA controller for controlling and measuring the bus... DMA controller for controlling and measuring the bus...

2007-12-04

2007-12-04

Peyton, Tammara (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S017000, C710S018000, C710S023000, C710S025000, C710S113000, C710S240000, C710S244000

Reexamination Certificate

active

10901294

ABSTRACT:
The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.

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Japanese Office Action issued in corresponding Japanese Patent Application No. JP 2003-285080, dated Jul. 12, 2006.

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