Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1998-10-01
2001-09-18
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S026000, C711S202000
Reexamination Certificate
active
06292853
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a DMA (direct memory access) controller, particularly of a type available for fast dealing with data block transfer between memory modules or elements.
For transferring data by DMA, a transfer circuit (channel) independent from a central processing unit (CPU) is formed, and a DMA controller is used to control it to enable direct exchange of data between different memory modules.
FIG. 1
is a block diagram showing connection between a DMA controller and a plurality of memory modules.
The DMA controller
70
is typically connected to a plurality of memory modules M
0
, M
1
, M
2
, . . . Mn, to transfer data between memory modules by exchanging an address signal, chip enable (CE) signal, read/write (R/W) signal, data read signal and data write signal with memory modules for data transfer.
FIG. 2
is a block diagram showing the construction of the DMA controller.
The DMA controller includes a source address generating circuit
82
, target address generating circuit
83
, chip enable (CE) signal generating circuit
84
, read/write (R/W) signal generating circuit
85
, address output circuit
86
, data read selecting circuit
87
, data holding register for temporarily holding transfer data, and state transition circuit
81
for controlling these circuits.
The state transition circuit
81
is connected to the source address generating circuit
82
, target address generating circuit
83
, chip enable (CE) signal generating circuit
84
, read/write (R/W) signal generating circuit
85
, and data read selecting circuit
87
, respectively. The source address generating circuit
82
is connected to the state transition circuit
81
, chip enable (CE) signal generating circuit
84
, address output circuit
86
and data read selecting circuit
87
, respectively. The target address generating circuit
83
is connected to the chip ennoble (CE) signal generating circuit
84
, read/write (R/W) signal generating circuit
85
and address output circuit
86
, respectively. The data read selecting circuit
87
is connected to the data holding register
88
. The data holding register
88
is connected to data write ports of all memory modules.
The address output circuit
86
decodes a source address and a target address on the basis of a predetermined address map, and functions as a switch for outputting the source address to the source-side memory and the target address to the target-side memory. It outputs “0”, for example, to a memory module which is neither the source nor the target.
The read/write (R/W) signal generating circuit
85
decodes a target address on the basis of the address map, and sets a read/write (R/W) signal to the target-side memory in the write state. At that time, the read/write (R/W) signal to the other memory modules is in the read state. Whether the DMA controller is in operation or not is determined by decoding the state variable from the state transition circuit
81
.
The chip enable (CE) signal generating circuit
84
decodes a source address and a target address on the basis of the address map, and sets a chip enable (CE) signal to a source memory module active in the state for reading from the source-side memory or sets the chip enable (CE) signal to a target memory module active in the state for writing to the target memory module. At that time, chip enable (CE) signals to the other memory modules are inactive. The state of reading from the source memory and the state of writing to the target memory are determined by decoding state variables from the state transition circuit
81
.
The state transition circuit
81
controls respective circuit blocks on the basis of a state transition diagram shown in
FIG. 8
, which will be explained later. Input signals to the state transition circuit
81
are a start signal from the exterior and an end signal from the source address generating circuit
82
. Output from the state transition circuit
81
is a state variable to the exterior, source address generating circuit
82
, target address generating circuit
83
and chip enable (CE) signal generating circuit
84
.
FIG. 3
is a timing chart of data transfer, and
FIG. 4
is a flow chart showing state transition during data transfer. With reference to
FIGS. 3 and 4
, operation of the DMA controller during data transfer is explained.
In the initial state 0, the DMA controller is in idling state (step S
101
). In the source address generating circuit
82
and the target address generating circuit
83
, the start address of data transfer and parameters such as the cycle are set. Until an external DMA start signal becomes active, the state 0 is held to be waiting, and the control proceeds to the next state 1 when the DMA start signal becomes active (step S
102
).
In the state 1, the address for reading out data of the first word is output to the source memory. Data is not read yet here (step S
103
).
In the state 3, the address for reading out data of the second word is output to the source memory, and the read-out data of the first word is output from the source memory and stored in the data holding register
88
(step S
104
).
In the state 7, addresses for reading out data are output sequentially to the source memory. On the other hand, input to the target memory are the write address and the data stored in the data holding register
88
. Data read out from the source memory is stored in the data holding register
88
(step S
105
). Before a read end signal from the source address generating circuit
82
to the state transition circuit
81
becomes active, the state 7 is repeated. When the read end signal becomes active, the flow progresses to the state 6 (step S
106
).
In the state 6, the address is not input to the source memory, but the final data is read out from the source memory. The address is input to the target memory, and the data of the second final ((n−1)th) from the final ((n)th) stored in the data holding register
88
is input to the target memory. The final data read out from the source memory is stored in the data holding register
88
(step S
107
).
In the state 4, the final data stored in the data holding register
88
is written in the target memory (step S
108
). Thereafter, the flow returns to the state 0.
By assigning state variables as explained above, decoding can be simplified as explained below when the state variables are expressed by binary numbers. That is, when the state variable bit
0
is 1 (in states 1, 3 and 7), and the address and the chip enable (CE) signal may be input to the source memory, and when bit
2
is 1(in states 4, 6 and 7), the address, chip enable (CE) signal and read/write (R/W) signal may be input.
FIG. 5
is a block diagram showing the construction of a source address generating circuit of a conventional DMA controller.
The source address generating circuit of the conventional DMA controller shown in
FIG. 5
is configured as follows. An effective address generator of the source address generating circuit includes a register
101
supplied with a base address (which is the first address in an address region for data to be transferred in the memory as the source of data) or the an increment to the preceding effective address, adder
106
supplied with the increment from the register
101
and the base address or the preceding effective address, and multiplexer
109
supplied with the base address and a result of calculation by the adder
106
to output one of them. A data counter of the source address generating circuit includes a register
104
in which the number of data to be transferred is set, adder
105
for adding the number of data to the prior transferred number of data every time upon transferring one unit of data, multiplexer
108
supplied with a result of calculation by the adder
105
to output the number of post-transfer data (0 when no data is transferred yet) to the register
102
, and comparator
107
for comparing the numbers of data output from the registers
102
and
104
.
Operations of the source address generating circuit of
FIG. 5
are as follows
Hogan & Hartson L.L.P.
Kabushiki Kaisha Toshiba
Lee Thomas
Mai Rijue
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