DMA channel for high-speed asynchronous data transfer

Details DMA channel for high-speed asynchronous data transfer DMA channel for high-speed asynchronous data transfer

2000-04-17

2004-04-27

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S025000, C710S029000, C710S032000, C710S053000, C710S058000, C709S241000, C713S500000

Reexamination Certificate

active

06728795

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to an apparatus for communication devices, in particular a DMA controller used for asynchronous data transfers of wireless communication data; such as Global System for Mobile communications (GSM), Code Division Multiple Access (CDMA), Personal Handy phone System (PHS) and Personal Digital Cellular (PDC).
2. Description of the Related Art
Recent advances in wireless communications have led to an explosion of cellular telephones. New telephones come in all shapes and sizes. Although the cellular phones come in different shapes and sizes, they generally share common elements such as a keypad, a display, an antenna and communication logic. What the cellular phones do not typically share however is the different global wireless communication standards that it must operate under.
The differing global wireless communication standards are typically determined by the wireless communications carrier, such as GTE Mobile (USA), SprintPCS (USA), AT&T Wireless (USA) and NTT Mobile (Japan). The differing communication standards include GSM, CDMA, PHS and PDC. The standards generally differ in multiplexing techniques, and operation frequencies. To accommodate the different standards, wireless phone manufacturers incorporate hardware and software that may be adaptable for the differing standards.
The hardware and software of the wireless telephone transmits and receives communication data. The wireless communication data is typically asynchronous and high speed in nature. Thus the hardware and software of the wireless telephone should be able to process the high speed asynchronous data.
Traditionally, a Universal Synchronous Asynchronous Receiver Transmitter (USART) is used to transmit and receive data. Traditional USARTs typically include one or two bytes of transmit or receive buffer memory. Although USARTs with more buffer memory are available, they generally are more expensive and will take more real estate on the silicon chip. As one skilled in the art is aware, chip real estate is at a premium. To adhere to the communications standards, the wireless telephone needs to be able to process the high speed asynchronous data. The use of the traditional USART generally would require more CPU power to process the high speed asynchronous data.
SUMMARY OF THE INVENTION
Briefly, an apparatus and method of a communications device, such as a wireless telephone for transferring high speed asynchronous data is disclosed. The apparatus includes a DMA controller, a DMA FIFO memory, timers, and a USART. The high speed asynchronous data is transmitted to and from the USART. The USART typically includes a small transmit and receive buffer, typically a one or two bytes buffer.
When the wireless telephone is in the receive mode, the asynchronous data is received by the USART. As the USART receive buffer receives data, the data is then transferred to a DMA FIFO. The size of the DMA FIFO can be any size, but preferably is eight bytes in size. Once the DMA FIFO is filled, data is then transferred to the DMA controller. The DMA controller will then transfer the data over a bus, such as a PCI bus, to a host memory. The data in host memory can be manipulated depending upon the communication standard configured for the wireless telephone. Since the data is asynchronous in nature, it is not certain whether or not data will be received by the USART to be processed by the DMA. Further, since the various communications standards may require a particular response to the incoming data in a time certain, the data should be processed within the time certain.
One of the bytes of the eight-byte DMA FIFO is a status byte. The status byte indicates the number of valid bytes in the DMA FIFO. Thus, should it be necessary to transfer to the DMA controller prior to the DMA FIFO having seven valid data bytes, the status byte will contain the number of bytes that are valid in the DMA FIFO. Should a timer expire, the data will be flushed from the DMA FIFO via the DMA controller for transfer to the host memory over a bus, such as a PCI bus.
When the wireless telephone is in the transmit mode, data from the host memory is transferred over a bus, such as a PCI bus to the DMA FIFO via a DMA controller. As previously discussed, one of the bytes is the status byte. The status byte includes information regarding the number of valid bytes in the DMA FIFO. The data in the DMA FIFO is then transferred to the USART transmit buffer for transmission. As previously discussed, if a timer expires, an interrupt is sent to the host memory so that data can be transferred via the DMA controller to the DMA FIFO.
In another embodiment, for GSM applications, two timers are included. The application of the first timer is similar to the description of the timer set forth above. The second timer is used in the GSM application, so that the wireless telephone can respond within a very short amount of time should it receive control data as part of the asynchronous data input. Since the wireless telephone needs to respond to the control data within a time certain, should the second timer expire, the second timer sends an interrupt to the host memory so that the data can be transferred by the DMA controller to the DMA FIFO for transmission by the USART.


REFERENCES:
patent: 5708659 (1998-01-01), Rostoker et al.
patent: 5794070 (1998-08-01), Rabe et al.
patent: 5912752 (1999-06-01), Mollett et al.
patent: 5958024 (1999-09-01), Typaldos et al.
patent: 6055578 (2000-04-01), Williams et al.
patent: 6105086 (2000-08-01), Doolittle et al.
patent: 6157972 (2000-12-01), Newman et al.
patent: 6230255 (2001-05-01), Asghar et al.
patent: 6425021 (2002-07-01), Ghodrat et al.
patent: 63262716 (1988-10-01), None
patent: 05028093 (1993-02-01), None
patent: 2000009861 (2000-01-01), None

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