DMA cache control logic

Details DMA cache control logic DMA cache control logic

1998-05-27

1999-12-14

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

711146, 710 22, G06F 1300

Patent

active

060031069

ABSTRACT:
A method and apparatus for snooping a host bridge. In a preferred embodiment, the apparatus includes a mechanism for loading data into the host bridge. Once the data is loaded, it is determined whether a copy of the data already resides in the host bridge. If so and the host bridge is not in the midst of a DMA transaction, the data will be immediately invalidated. If the host is in the midst of a DMA transaction, the data is then marked for invalidation.

REFERENCES:
patent: 5072369 (1991-12-01), Theus et al.
patent: 5214767 (1993-05-01), Wanner et al.
patent: 5247648 (1993-09-01), Watkins et al.
patent: 5359723 (1994-10-01), Mathews et al.
patent: 5530933 (1996-06-01), Frink et al.
patent: 5544345 (1996-08-01), Carpenter et al.
patent: 5551006 (1996-08-01), Kulkarni
patent: 5555398 (1996-09-01), Raman
patent: 5561820 (1996-10-01), Bland et al.
patent: 5579530 (1996-11-01), Solomon et al.
patent: 5623700 (1997-04-01), Parks et al.
patent: 5630094 (1997-05-01), Hayek et al.
"Demi" Cache Management Policy for a Coherent DMA Cache on a Snooping Memory Bus, IBM Technical Disclosure Bulletin, vol. 37, No. 06A, Jun. 1994, pp. 241-242.
Concurrent Register Loading From Memory and register Storing to I/O, IBM Technical Disclosure Bulletin, vol. 36 , No. 1, Jan. 1993, pp. 395-396.
Data Transfer for PIO To/From System Memory Using Streaming Data Protocol, IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990, p. 300.
Direct Memory Access for Multiple Requesting Computer Device, IBM Technical Disclosure Bullertin, vol. 31, No. 11, Apr. 1989, pp. 324-328.
Cache Coherency Data Alignment, Research Disclosure, Jan. 1990, No. 309.

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