Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
2000-06-22
2003-11-25
Gaffin, Jeffrey (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S023000, C710S026000, C710S028000, C710S305000, C710S308000, C710S314000, C711S202000, C711S210000
Reexamination Certificate
active
06654818
ABSTRACT:
BACKGROUND
1. Field of the Present Invention
The present invention generally relates to the field of input/output (I/O) busses and more particularly to a protection method and mechanism suitable for use in a 64-bit addressing system that includes a 64-bit I/O adapter.
2. History of Related Art
In the field of microprocessor based data processing systems, the use of industry standard I/O busses to improve the performance and expand the capabilities of the data processing systems is well known. Standardized I/O busses provide a mechanism for connecting a wide variety of peripheral devices to the host bus of a data processing system. Peripheral devices may include, for example, high speed network adapters, hard-disk controllers, graphics adapters, audio adapters, and a variety of other devices. Among the most prevalent of the industry standard I/O busses is the Peripheral Component Interface (PCI) bus. The PCI bus has evolved over the years from revision 2.0 introduced in 1992 operating at a bus frequency of 33 MHz, to revision 2.1 introduced in 1995 with a maximum bus frequency of 66 MHz, to revision 2.2 introduced in 1998 and incorporating features such as message interrupts. Complete documentation of the PCI Local Bus Specification Rev. 2.2 (PCI Spec 2.2) is available from the PCI special interest group, 2575 N. E. Kathryn #17, Hillsboro, Oreg. 97124 (website www.pcisig.com). Under PCI Spec 2.2, PCI bridges support two types of transactions: posted transactions (including memory write cycles), which complete on the initiating bus before they complete on the target bus, and delayed transactions (including memory read requests and I/O and configuration read/write requests), which complete on the target bus before they complete on the initiating bus. A PCI device that initiates a delayed transaction must relinquish control of the local PCI bus and wait for the target device to return the requested data (in the case of a delayed read request) or a completion message (in the case of a delayed write request). Once the requested information has arrived, the requesting device must wait until it again receives control of the PCI bus in the normal course of operations before it can retrieve the information from the PCI bridge.
More recently, the PCI-X Addendum to Local Bus Specification Rev. 2.2 has been proposed as a means for further improving the performance of PCI busses. The PCI-X Addendum incorporates registered transactions that improve performance by permitting a PCI-X compatible bridge or I/O adapter to make decisions on every other clock cycle. In addition, PCI-X incorporates protocol enhancements such as the attribute phase and split transactions that allow more efficient use of the bus. PCI-X is fully backward compatible with conventional PCI systems such that conventional PCI adapters will work in PCI-X capable systems and PCI-X adapters will work in PCI systems. If a conventional PCI device is located on a PCI-X bus, however, all adapters on the bus must operate in conventional PCI mode regardless of whether they are PCI-X capable. For complete PCI-X documentation, the reader is referred to the PCI-X Addendum 1.0 Final Release available from the PCI Special Interest Group.
A high percentage of I/O adapters (IOA's) support a maximum of 32 address bits. Such adapters are capable of addressing only 4 GB of system memory address space. With increasing frequency however, these 32-bit I/O adapters are installed in systems that support 64-bit addressing. IOA's that are only cable of accessing 4 GB need a way to access above that limit when used in 64-bit addressing systems when the addressing requirements exceed the 4 GB limit. This could be accomplished with a device driver that transfers the data to a DMA buffer within the first 4 GB of system memory and then re-transferring the data to memory residing above 4 GB with a software data move. This solution, however, may have a significant impact on performance and it is in these larger systems where performance is generally the most critical. To address this problem, the use of Translation Control Entry (TCE) tables are used to facilitate the translation of DMA addresses generated by 32-bit I/O adapters in systems that support addressing of more than 32-bits. In addition, the TCE table provides status bits for each entry that are used to enforce memory protection. If the protection status bits of a particular TCE have a specified value, an IOA will be unable to access the portion of system memory address space that corresponds to the entry.
The use of TCE tables in conventional systems, while addressing the problem of address translation between IOA's and system memory, can potentially limit performance in systems that also include IOA's that support 64-bit addressing. Although no address translation is needed for addresses generated by 64-bit IOA's, conventional systems may force the address generated by a 64-bit adapter through the TCE mechanism to utilize the protection mechanism provided by the TCE table. The use of extensive TCE tables that typically have limited granularity (i.e., each TCE corresponds to a small portion of the memory address space) is an inefficient method of implementing protection for 64-bit IOA's because the translation bits in each TCE are unnecessary for 64 bit I/O adapters. In addition, the relatively small page size associated with each TCE may result in excess retrieval of the TCE (which typically resides in system memory) thereby potentially limiting performance. It would therefore be desirable to implement an efficient protection mechanism in a data processing system that includes 64-bit IOA's.
SUMMARY OF THE INVENTION
The problem identified above is addressed by a method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter as disclosed herein. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus such as a PCI bus. A first I/O adapter, which generates 32-bit addresses, may be coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width. greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes one or Access Control Tables (ACTs). An ACT determines whether DMA access to the system memory address generated by a 64-bit I/O adapter is authorized. The ACT may be formatted as a set of ACT entries where each ACT entry corresponds to a unique portion of the system's memory address space. In one embodiment, each ACT entry consists of a single bit that indicates access to a 256 MB or larger portion of the system memory address space. The first and second I/O adapters may be connected to a secondary PCI bus that communicates with the primary PCI bus via a PCI-to-PCI bridge. In one embodiment, each 64-bit I/O adapter has its own ACT table and portions of the ACT table may reside in the PCI-to-PCI bridge.
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Gaffin Jeffrey
McBurney Mark E.
Patel Niketa
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