DLL with reduced size and semiconductor memory device...

Details DLL with reduced size and semiconductor memory device... DLL with reduced size and semiconductor memory device...

2006-09-28

2009-06-02

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S193000, C365S201000

Reexamination Certificate

active

07542358

ABSTRACT:
A delay locked loop(DLL) includes a phase detector for detecting phase difference between input clock signals and feedback clock signals, and outputting phase detection signals according to results of the detection, a delay line for delaying the input clock signals in response to first and second delay control signals, and outputting delay clock signals, a delay controller for generating the first and the second delay control signals in response to the phase detection signals, and a delay model for delaying reference clock signals during predetermined time, and outputting the delayed signals as the feedback clock signals.

REFERENCES:
patent: 5956290 (1999-09-01), Matsuzaki
patent: 6765976 (2004-07-01), Oh
patent: 7212465 (2007-05-01), Kang
patent: 1020010091534 (2001-10-01), None
patent: 1020040064862 (2004-07-01), None
patent: 1020040095981 (2004-11-01), None
patent: 1020060079581 (2006-07-01), None
Notice of Allowance for Korean App. 2006-43322.

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