Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-12-27
2004-11-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S230030
Reexamination Certificate
active
06813197
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a DLL driving circuit for effectively resetting a DLL and a method for driving the same.
DESCRIPTION OF THE PRIOR ART
A semiconductor memory device such as a dynamic random access memory (DRAM) operates in synchronization with a row address strobe signal (/RAS) and a column address strobe signal (/CAS), so that there is a limitation in an access speed. Therefore, in particular, a single data rate (SDR) SDRAM is widely used in systems requiring a high speed. Here, the SDRAM is a synchronous memory device which operates in synchronization with rising edges of a system clock. Currently, the SDR SDRAM is a typical memory and 256M/512M memory devices have been developed. A development of 1G memory devices tends to be advanced. As is well known, in addition to the development of the synchronous semiconductor memory device, an operating speed of the semiconductor memory device also becomes faster.
The high-speed tendency is progressed much more with an advent of a double data rate (DDR) SDRAM designed to be operable at both rising edges and falling edges of the system clock. Now, an operating speed of the DDR SDRAM is about several hundreds MHz. As is well known, the DDR SDRAM performs write and read operations at rising and falling edges, respectively. Two data per one clock are processed. In other words, data is written or read at the rising edge and the falling edge, respectively.
As a semiconductor memory device applicable to the system clock is demanded, the DDR SDRAM becomes a main stream as a next-generation memory device. In addition, it is no wonder that it is necessary to implement a reliable operation.
Meanwhile, a clock generation circuit (i.e., a delay locked loop) for compensating for a skew between an external clock and a data or a skew between an external clock and an internal clock is installed in on-chip. At this time, the DLL can be used in a semiconductor memory device of a packet command drive type, such as Rambus DRAM. The DLL is a necessary circuit employed in a high-speed memory device such as the DDR SDRAM. In addition, the DLL is a circuit for solving a timing delay of a clock.
For driving the DLL, a DLL driving circuit of
FIG. 1
is needed.
Generally, a conventional DLL driving circuit includes a DLL reset signal generator
100
and a disable-DLL signal generator
200
. The DLL reset signal generator
100
is driven in response to a bank selection address BANK
0
, an address A
8
and a mode register set signal MRSP. Here, the address A
8
is a signal outputted from an address input buffer (not shown), and the mode register set signal MRSP is a signal outputted from a command decoder (not shown). At this time, “P” of the reference symbol MRSP means a pulse signal.
The disable-DLL signal generator
200
is driven in response to a coded bank selection address BANK
1
, the mode register set signal MRSP and an address A
0
. Here, the disable-DLL signal generator
200
includes an RGWT signal generation unit
200
A and a DIS_DLL signal generation unit
200
B under the consideration of an output signal generating sequence. The RGWT signal is a read/write signal. A detailed configuration of the disable-DLL signal generator
200
can be also implemented with other logic structure.
Hereinafter, an operation of the conventional DLL driving circuit shown in
FIG. 1
will be described in detail. In order to drive the DLL, commands are inputted in an arbitrarily defined order in a power-up sequence. In other words, after a power-on, the DLL is enabled in response to an extended mode register set signal (EMRS). Here, the extended mode register set signal (EMRS) is a signal obtained by extending the mode register set signal MRSP signal to the bank address. The DLL is reset in response to the mode register set signal MRSP. In other words, after the power-on, the bank selection signal is enabled in response to a combination of bank addresses BA
0
and BA
1
, and the DLL is enabled in response to the address A
0
(A
0
=0). Then, the DLL is reset in response to the mode register set signal MRSP and the address A
8
(A
8
=1) through an operation of the DLL reset signal generator
100
. Generally, the DLL reset signal (DLL_RESET) is generated in a high pulse form in order for the reset operation.
Meanwhile, in case of a certain chipset manufacturer, a chip controller does not employ an MRSP command, i.e., a mode register set signal for the DLL reset. In this case, it is impossible to perform the reset operation using the MRSP signal (i.e., an input signal of the DLL reset signal generator
100
shown in FIG.
1
). Therefore, the DLL is not initialized, so that chip performance such as DLL locking time is badly affected. In addition, there occurs a problem that a possibility of DLL fail occurrence increases in its installation.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a DLL driving circuit of a semiconductor memory device and a method for driving the DLL, capable of minimizing a DLL failure in installation and improving a chip performance.
Another object of the present invention is to provide a DLL driving circuit and a method for driving the DLL, in which the DLL driving circuit resets the DLL regardless of an input of a mode register set signal.
Further another object of the present invention is to provide a DLL driving circuit and a method for driving the DLL, in which the DLL driving circuit drives the reset of the DLL from a DLL enable command.
In accordance with an aspect of the present invention, there is provided a DLL driving circuit for use in a semiconductor memory device, which comprises: a DLL reset signal generation means for receiving a first bank selection address; a disable-DLL signal generation means for receiving a second bank selection address and a mode register set signal; and a reset driving means for receiving the disable-DLL signal outputted from the disable-DLL signal generation means and driving the DLL reset signal generation means.
Further, in accordance with another aspect of the present invention, there is provided a method for driving a DLL of a semiconductor memory device, which comprises the steps of: a) receiving a first bank selection address and generating a DLL reset signal; b) receiving a second bank selection address and a mode register set signal and generating a disable-DLL signal; and c) controlling a driving of the DLL reset signal in response to the disable-DLL signal, wherein the DLL reset is driven through the step c) if the mode register set signal for resetting the DLL is not inputted.
REFERENCES:
patent: 6215726 (2001-04-01), Kubo
patent: 6418068 (2002-07-01), Raynham
patent: 6552955 (2003-04-01), Miki
patent: 2002/0017939 (2002-02-01), Okuda et al.
patent: 2002/0130691 (2002-09-01), Silvestri
patent: 2002/0136082 (2002-09-01), Chu et al.
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