DLL circuit, imaging device, and memory device

Details DLL circuit, imaging device, and memory device DLL circuit, imaging device, and memory device

2011-03-29

2011-03-29

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S076000, C365S233120, C327S144000, C327S145000, C327S147000, C327S149000, C327S152000, C327S153000, C327S158000, C327S156000, C327S161000, C327S163000

Reexamination Certificate

active

07916561

ABSTRACT:
A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit.

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