DLL circuit and a memory device building the same in

Details DLL circuit and a memory device building the same in DLL circuit and a memory device building the same in

1998-06-19

1999-09-21

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365157, 365158, G11C 800

Patent

active

059562900

ABSTRACT:
A non-loop type DLL circuit which makes it possible to lock in at accurate timing for a short time and a memory device in which the DLL circuit is built in. The above-described clock cycle measurement section measures a clock cycle of a reference clock plural times and generates a delay control signal according to the coincident result while the plural measurements. The variable delay circuit is supplied with a reference clock or an internal clock (first clock) maintaining the same clock cycle delayed by a prescribed phase from the reference clock, and its delay time is controlled according to the delay control signal so that it generates at an output terminal an output clock (second clock) in synchronism with the reference clock and maintains a prescribed phase relationship with the reference clock.

REFERENCES:
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5550514 (1996-08-01), Liedberg
patent: 5581512 (1996-12-01), Kitamura
patent: 5796673 (1998-08-01), Foss et al.
patent: 5825226 (1998-10-01), Ferraiolo et al.
SP23.4: A 2.5ns Clock Access 25O MHz 256Mb SDRAM with a Synchronous Mirror Delay, SAEKI et al., IEEE International Solid-State Circuits Conference, Feb. 10, 1996, pp. 374-375.

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