DLL circuit

Details DLL circuit DLL circuit

2006-03-28

2006-03-28

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C375S373000, C375S327000, C327S102000, C327S147000, C327S159000, C331S00100A

Reexamination Certificate

active

07020228

ABSTRACT:
A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generator for generating a constant current source bias signal for controlling the constant current source of the functional block, the bias generator comprising a bias control which changes the bias signal according to the frequency of the input signal.

REFERENCES:
patent: 4438353 (1984-03-01), Sano et al.
patent: 5886946 (1999-03-01), Ooishi
patent: 6198332 (2001-03-01), O'Toole et al.
patent: 6239633 (2001-05-01), Miyano
patent: 6285725 (2001-09-01), Sung et al.
patent: 9-17179 (1997-01-01), None
patent: 9-512966 (1997-12-01), None
patent: 1998-056057 (1998-09-01), None
Low-jitter process-independent DLL and PLL based on self-biased techniques, Maneatis, J.G.; Solid-State Circuits, IEEE Journal of, vol.: 31, Issue: 11, Nov. 1996, pp.: 1723-1732.
Korean Office Action dated Dec. 18, 2002.
Japanese translation of Korean Office action dated Dec. 16, 2002.
English transaltion of Japanese translation.

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