Divider circuit adopting a neural network architecture to increa

Details Divider circuit adopting a neural network architecture to increa Divider circuit adopting a neural network architecture to increa

1990-07-09

1992-07-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

051309440

ABSTRACT:
A divider circuit for efficiently and quickly performing a hardware implemented division by adopting a neural network architecture. The circuit includes a series of cascaded subtracter components that complement the divisor input and effectively perform an adder function. The subtracters include a synaptic configuration consisting of PMOS transistors, NMOS transistors, and CMOS inverters. The components are arranged in accordance with the predetermined connection strength assigned to each of the transistors and its respective position in the neural type network arrangement.

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